Abstract: Systems, methods, and devices are disclosed herein for developing a cell design. Operations of a plurality of electrical cells are simulated to collect a plurality of electrical parameters. A machine learning model is trained using the plurality of electrical parameters. The trained machine learning model receives data having cell layout design constraints. The trained machine learning model determines a cell layout for the received data based on the plurality of electrical parameters. The cell layout is provided for further characterization of electrical performance within the cell layout design constraints.

Abstract: A modular battery storage system includes energy storage modules. A switch is assigned to individual energy storage modules, by which the respective energy storage module can be activated and deactivated. The energy storage modules can connect to one another by the switches such that the individual voltages of activated energy storage modules can be added up to form a total voltage. A method of operating the battery storage system ascertains at least one power value for each of the energy storage modules, the power value being characteristic of the power capacity of the energy storage module. A total voltage is generated by at least two energy storage modules being activated with a time overlap but over activation periods of different length. One of the activation periods of different length is assigned to each of the at least two energy storage modules depending on the ascertained at least one power value.

Abstract: A power conversion device for charging a battery of a vehicle may include the battery, a motor for receiving a battery power source from the battery, a power controller for controlling the motor to change the battery power source into charging power, and a charging controller for selectively performing a charging power supply control for supplying the charging power to the outside and a charging power receipt control for receiving external power.

Abstract: Devices, systems, and methods for coupling with an implantable neurostimulator for delivering one or more electrical pulses to a target region within a patient's body are disclosed herein. A device, such as a charger, can include: a power source for storing electrical energy; a resonant circuit that can have a plurality of selectable natural frequencies; a driver coupled to the power source and the resonant circuit; and a processor coupled to the resonant circuit to control the natural frequency of the resonant circuit. The processor can control the natural frequency of the resonant circuit according to stored data associated with the implantable neurostimulator.

Abstract: Described are various embodiments of a system and method for verifying extracted integrated circuit (IC) features representative of a source IC and stored in a feature dataset structure. Generally, a set of extracted IC features imaged within a designated IC area is converted into a static tile image. The static tile image is then rendered for visualization as an interactive mapping of the feature dataset structure within the area. Corrections for one or more of the set of extracted IC features are received based on the static tile image and input corrections are executed on the feature dataset structure to produce an updated feature dataset structure.

Abstract: Bit-reduction in a verification processes for memory arrays is disclosed. Properties are determined for verification of a circuit that includes a memory array. Circuit data for the circuit is received in a verification environment. When it is determined that the circuit includes a memory array, an address for the memory array is sampled as part of a read operation during verification for the circuit. A determination may be made that the circuit is in compliance with a property of the properties based at least in part on compliance of the read operation with a predetermined model. The sampling of the address replicates a delay expected in physical read operation of the memory array, but with reduced bits communicated or generated per cycle in the verification process because output data is not sampled contrasting the physical read operation.

Abstract: The present disclosure is directed to a battery charger capable of charging a plurality of battery packs. The charger includes the ability to cool electronic components of the charger with a first fan and to cool the battery packs with a set of second fans.

Abstract: A charging case for charging and storing a pair of earbuds is provided. The charging case comprises: a case body having an upper section and a lower section, the lower section housing at least a battery and a PCB, the upper section having a pair of sockets to accommodate the pair of earbuds, respectively; and a USB cable comprising a distal end portion including a USB connector, a cable body housing electrical wires coupled to the USB connector, and a proximal end portion non-removably attached to the case body. The electrical wires are guided through the housing wall into an inner space of the case body where end portions of the electrical wires are soldered onto the PCB. A recessed area is formed on the exterior surface of the case body to accommodate the attached USB cable while not in use.

Abstract: A chip includes a substrate; macros placed on the substrate, which has a placement region being divided into sub-regions according to locations of the macros; and one or more vertical power stripes (VPSs) disposed in each sub-region. At least one VPS is not aligned with the VPSs of an adjacent higher or lower sub-region.

Abstract: A computerized system is disclosed. The computerized system may include one or more processors configured to perform the operations stored in a memory. The operations may include receiving a first circuit design pattern including a DRC violation and generating a first pattern matrix based on the first circuit design pattern, and updating the first circuit design pattern, based on the first pattern matrix, to fix the DRC violation. The operations may also include determining a possibility of a DRC violation-free first circuit design pattern corresponding to the first pattern matrix, and generating a first target label specifying the fixability corresponding to the first pattern matrix based on the determined possibility of the DRC violation-free first circuit design pattern. The first pattern matrix and the first target label may be used as training data to train a machine-learning model to predict fixability of the DRC violation.

Abstract: A semiconductor device includes: active regions arranged in a first grid oriented substantially parallel to a first direction; and gate electrodes arranged spaced apart in a second grid and overlying corresponding ones of the active regions, the second grid being oriented substantially parallel to a second direction, the second direction being substantially orthogonal to the first direction. The first gaps are interspersed correspondingly between neighboring ones of the active regions. For a flyover intersection at which a corresponding gate electrode crosses over a corresponding active region and for which the gate electrode is not functionally connected to the corresponding active region, the gate electrode does not extend substantially beyond the corresponding active region and so does not extend substantially into a corresponding one of the first gaps.

Abstract: Techniques for net routing for an integrated circuit (IC) design are described herein. An aspect includes receiving a netlist corresponding to a net in an IC design. Another aspect includes identifying intermediate logic in the net, wherein the intermediate logic is connected between a source and a sink of the net, and wherein the sink is located downstream from the source in the IC design. Another aspect includes hiding the intermediate logic from the netlist. Another aspect includes creating a global route in the IC design between the source and the sink of the net without the intermediate logic. Another aspect includes restoring the intermediate logic to the netlist. Another aspect includes placing the intermediate logic along the global route.

Abstract: A logic element includes a logic block, a supply voltage input, switchable power gates and a gate selector. The logic block implements a logic function on input data to obtain at least one output data signal. The switchable power gates transfer a supply voltage from the supply voltage input to the logic block in accordance with respective gate control signals. At least two of the power gates have different respective electrical properties. The gate selector switches on differing ones of the power gates in accordance with gate selection data.

Abstract: A reusable battery indicator includes a voltage sensor configured to convert sensed analog characteristics of a battery to digital information; a communication circuit communicatively connected to the voltage sensor; an antenna operatively coupled to the communication circuit; and a connection mechanism having at least a first connector and a second connector that are electrically connected to the voltage sensor, the first connector and the second connector being adapted to be removably connected to a first battery terminal and to a second battery terminal, respectively, thereby completing an electrical circuit between the voltage sensor and the first and second battery terminals when the connection mechanism is coupled to the first battery terminal and to the second battery terminal. One or more of the first connector and the second connector include part of a mechanical lock and key assembly.

Abstract: Systems and methods for operating an electric energy storage system are described. The systems and methods include ways of coupling electric energy storage cell stacks to an electric conductor or bus. The coupling is performed to reduce current flow through contactors and to increase a life span of the contactors.

Abstract: In an example, an apparatus comprises a compute engine comprising a high precision component and a low precision component; and logic, at least partially including hardware logic, to receive instructions in the compute engine; select at least one of the high precision component or the low precision component to execute the instructions; and apply a gate to at least one of the high precision component or the low precision component to execute the instructions. Other embodiments are also disclosed and claimed.

Abstract: Techniques to improve the accuracy and speed for detection and remediation of difficult to test nodes in a circuit design netlist. The techniques utilize improved netlist representations, test point insertion, and trained neural networks.

Abstract: Methods for place-and-route aware data pipelining for an integrated circuit device are provided. In large integrated circuits, the physical distance a data signal must travel between a signal source in a master circuit block partition and a signal destination in a servant circuit block partition can exceed the distance the signal can travel in a single clock cycle. To maintain timing requirements of the integrated circuit, a longest physical distance and signal delay for a datapath between master and servant circuit block partitions can be determined and pipelining registers added. Datapaths of master circuit block partitions further away from the servant circuit block can have more pipelining registers added within the master circuit block than datapaths of master circuit block partitions that are closer to the servant circuit block.

Abstract: Provided herein are systems and methods for optimizing feature fill processes. The feature fill optimization systems and methods may be used to optimize feature fill from a small number of patterned wafer tests. The systems and methods may be used for optimizing enhanced feature fill processes including those that include inhibition and/or etch operations along with deposition operations. Results from experiments may be used to calibrate a feature scale behavioral model. Once calibrated, parameter space may be iteratively explored to optimize the process.

Abstract: A structure includes first, second, third, and fourth conductive segments, and a gate. The first and second conductive segments are in a first conductive layer and configured as first and second terminals of a first transistor of a first type. The third and fourth conductive segments are in a second conductive layer stacked over the first conductive layer and configured as first and second terminals of a second transistor of a second type. The first gate is arranged, in a first direction, between the first and third conductive segments and the second and fourth conductive segments. The gate is configured as a control terminal of the first transistor and a control terminal of the second transistor, the first conductive segment is offset from the third conductive segment along the first direction, and the second conductive segment is offset from the fourth conductive segment along the first direction.