Patents Examined by Brian Pendelton
  • Patent number: 6782108
    Abstract: Audio signals of a plurality of input channels are received via corresponding input terminals. First adjusting section adjusts respective volume levels of the audio signals received via the input channels. First mixing section mixes the audio signals, having been adjusted in volume level by the first adjusting section, to thereby provide a mixed signal. The mixed signal is distributed to a plurality of channels. Second adjusting section also adjusts respective volume levels of the audio signals received via the input channels. For each of the channels, a second mixing section mixes the received audio signal, having been adjusted in volume level by the second adjusting section, with the mixed signal distributed to that channel. Thus, for each of the channels, there is provided an output signal comprising a mixture of the received audio signal and the mixed signal. The thus-provided output signals can be listened to or monitored via headphones or the like on a channel-by-channel basis.
    Type: Grant
    Filed: November 1, 2002
    Date of Patent: August 24, 2004
    Assignee: Yamaha Corporation
    Inventor: Koichiro Shibata
  • Patent number: 6430287
    Abstract: A combined, parallel adaptive equalizer/echo canceller is disclosed. The equalizer/canceller receives at least one input signal which is split into n taps. The n taps are multiplied by corresponding n tap coefficients to produce n tap output signals. The n tap output signals are then processed through an additive pipeline to produce a filter output signal. The additive pipeline provides low latency by processing the nth most recent tap output signal n clock cycles from the filter output signal. The combined FIR filter structure is made fully adaptive using delayed LMS coefficient adaptation. Tap coefficients are updated using an error signal and delayed versions of the input signal. The error signal is a product of a calculated error and a negative adaptation factor. The delay is equal to a sum of n+1 cycles.
    Type: Grant
    Filed: August 28, 1997
    Date of Patent: August 6, 2002
    Assignee: Level One Communications, Inc.
    Inventor: Sailesh Krishna Rao