Patents Examined by Brook Kebide
  • Patent number: 6316359
    Abstract: In one embodiment, a conductive interconnect (38) is formed in a semiconductor device by depositing a dielectric layer (28) on a semiconductor substrate (10). The dielectric layer (28) is then patterned to form an interconnect opening (29). A tantalum nitride barrier layer (30) is then formed within the interconnect opening (29). A catalytic layer (31) comprising a palladium-tin colloid is then formed overlying the tantalum nitride barrier layer (30). A layer of electroless copper (32) is then deposited on the catalytic layer (31). A layer of electroplated copper (34) is then formed on the electroless copper layer (32), and the electroless copper layer (32) serves as a seed layer for the electroplated copper layer (34). Portions of the electroplated copper layer (34) are then removed to form a copper interconnect (38) within the interconnect opening (29).
    Type: Grant
    Filed: February 4, 2000
    Date of Patent: November 13, 2001
    Assignee: Motorola Inc.
    Inventor: Cindy Reidsema Simpson