Abstract: A method of manufacturing a top-gate self-aligned thin film transistor involves the use of back exposure of a negative resist (26) using the lower source and drain electrode pattern (11, 12) as a photomask. A transparent amorphous silicon layer (24) is used as the gate electrode layer of the TFT structure, and the resistance of this gate electrode layer (24) is reduced by subsequent processing. For example, a silicide layer (32) may be formed over the gate electrode layer (24) which has the added advantage of reducing the transparency of the insulated gate structure (22, 24) of the TFT, thereby reducing the dependency of the TFT characteristics on light conditions.

Abstract: A method of interconnecting electronic components by using a plurality of conductive studs on a surface of a first electronic component and a plurality of corresponding conductive vias on the surface of a second electronic component. Camber on the surface of electronic components may be overcome by coating the surface with a dielectric, planarizing the dielectric, and forming conductive vias corresponding to the contact pads thereon. The conductive studs are substantially lead-free and preferably comprise of copper.