Patents Examined by Bruce E. Hearn
  • Patent number: 5024956
    Abstract: A method of manufacturing a semiconductor device having a monocrystalline silicon region (3) comprising a first zone (9) and an adjacent second zone (10) and laterally enclosed by a sunken oxide layer (4) and by an overlying highly doped polycrystalline silicon layer (5). The silicon layer (5) is laterally separated by an oxide layer (6) from the silicon region (3) and adjoins the first zone (9) on a narrow edge portion of the upper surface of the region (3), this zone being of the same conductivity type as the silicon layer (5). The second zone (10) is provided with an electrode layer (11). According to the invention, the silicon layer (5) is separated from the electrode layer (11) by an oxide strip (12A) formed in a self-aligned manner and at least one doped connection zone (13) having a width determined by said oxide strip (12A) is situated between said first and said second zones and located below said oxide strip (12A).
    Type: Grant
    Filed: June 7, 1990
    Date of Patent: June 18, 1991
    Assignee: U.S. Philips Corporation
    Inventors: Johannes W. A. Van Der Velden, Henricus G. R. Maas, Marguerite M. C. Van Iersel-Schiffmacher