Abstract: Some embodiments provide a method for calculating parasitic parameters for a pattern to be manufactured on an integrated circuit (IC) substrate. The method receives a definition of a wire structure as input. The method rasterizes the wire structure (e.g., produces pixel-based definition of the wire structure) to produce several images. Before rasterizing the wire structure, the method in some embodiments decomposes the wire structure into several components (e.g., several wires, wire segments or wire structure portions), which it then individually rasterizes. The method then uses the images as inputs to a neural network, which then calculates parasitic parameters associated with the wire structure. In some embodiments, the parasitic parameters include unwanted parasitic capacitance effects exerted on the wire structure. Conjunctively, or alternatively, these parameters include unwanted parasitic resistance and/or inductance effects on the wire structure.

Abstract: A first set of features may be extracted from a first integrated circuit (IC) design. A trained machine learning (ML) model may predict a set of ranked test-case configurations for the first IC design based on the first set of features. A test-case configuration may correspond to a count of scan chain input and output ports and a scan chain length value.

Abstract: In some embodiments, a method for designing a photonic device is provided. A design optimization system receives an initial design for the photonic device. The initial design includes one or more inputs, one or more outputs, a number of subcomponent regions, and a number of waveguides for connecting the subcomponent regions. The design optimization system simulates each subcomponent region to determine simulated s-parameters of each subcomponent region. The design optimization system determines overall s-parameters for a simulated photonic device based on the simulated s-parameters of each subcomponent region and s-parameters of the waveguides. The design optimization system determines an overall gradient associated with the overall s-parameters. The design optimization system optimizes one or more subcomponent regions based on the overall gradient to create an updated design for the photonic device.

Abstract: A digital pattern generation system comprises a memory and a controller. The controller is coupled the memory and is configured to remove redundant cells from a digital pattern file, generate a first updated digital pattern file and compare the first updated digital pattern file with the digital pattern file. Further a number of vertexes of a first arc of the first updated digital pattern file is reduced to generate a second updated digital pattern file. Additionally, a first cell of the second updated digital pattern file is replaced with an alternative version of the first cell to generate a third updated digital pattern file. Further, one or more polygons within the third updated digital pattern file is converted to one or more quad polygons to generate an optimized digital pattern file.

Abstract: The present disclosure relates to a method and apparatus for determining a relative energy between systems, an electronic device, a computer-readable storage medium, and a computer program product. The method includes: for a chemical system, performing a plurality of iteration rounds using a neural network variational Monte Carlo method; acquiring a linear relationship between energy errors and energy variances, which are obtained in the plurality of iteration rounds; determining a first energy error at a position where the energy variance is zero based on the linear relationship; and determining the relative energy between the chemical system and a further system based on the first energy error.

Abstract: Embodiments are provided for enhanced initial global placement in a circuit design in a computing system by a processor. A wire length minimization may be determined based on maximum population density constraints as a single player game theory for global placement of an integrated circuit.

Abstract: Some embodiments include apparatuses and electrical models associated with the apparatus. One of the apparatuses includes an integrated circuit having a die; a package substrate; first conductive connections coupled between the die and a first side of the package substrate; second conductive connections located on a second side of the package substrate opposite from the first side. The second conductive connections are coupled to the first conductive connections through conductive paths in the package substrate. The first conductive connections and the conductive connections are associated with an S-parameter of an electrical model of the integrated circuit package. The electrical model further includes at least one of a current value associated with a power rail of the integrated circuit package, an impedance target associated with a location at the integrated circuit package, and a mapping associated with the first and second conductive connections.

Abstract: A computerized method for generating a 3D Computer-Aided Design (CAD) is provided. The method comprising: receiving an input comprising requirements for a new design; processing the input to generate a CAD design using a trained AI model, wherein the CAD design is an assembly of at least two separate components; and outputting the CAD design.

Abstract: The external heterogeneity in the Discrete Event System Specification (DEVS) for simulators refers to the ability to incorporate different types of models, each with potentially different behaviors, into a single simulation environment. In the DEVS framework, a system is composed of multiple individual models, each representing a component of the system. These models can be either atomic (cannot be decomposed further) or coupled (composed of other models). This gives DEVS its hierarchical nature. The atomic or coupled models can in DEVS Markov models be fundamentally different from each other. For example, one model might represent a deterministic rule-based decision process, while another model might represent a probabilistic random variable generator. These models have different state variables, different event sets, and different transition functions, but they can still interact with each other within the same simulation.

Abstract: The present disclosure provides a method and an apparatus for testing a semiconductor device. The method includes providing an active area in an integrated circuit design layout; grouping the active area into a first region and a second region; calculating a first self-heating temperature of the first region of the active area; calculating a second self-heating temperature of the second region of the active area; and determining an Electromigration (EM) evaluation based on the first self-heating temperature and the second self-heating temperature.

Abstract: A computerized method for generating a 3D Computer-Aided Design (CAD) is provided. The method comprising: receiving an input comprising requirements for a new design; processing the input to generate a CAD design using a trained AI model, wherein the CAD design is an assembly of at least two separate components; and outputting the CAD design.

Abstract: A method includes: receiving a simulation vector associated with a circuit design, wherein the simulation vector is associated with a simulation vector type; identifying, by a processor, a plurality of glitch transitions from among one or more transitions associated with a pin of a cell of the circuit design during a clock period of the simulation vector, and determining a glitch power consumption of the cell during the clock period based on the plurality of glitch transitions.

Abstract: A prediction system includes a charger and an estimation apparatus, and performs a method of predicting capacity degradation of a secondary battery. The estimation apparatus obtains changes of a plurality of parameters of capacity degradation, based on a fitting operation of fitting, to a target-battery charge curve of a target battery, reference data of the target battery or a battery of the same type as the target battery. Further, the estimation apparatus identifies a degradation change point where the degradation speed of the maximum battery capacity becomes high as a result of increase of the usage degree of the target battery, based on the plurality of obtained parameters.

Abstract: A method for predicting a property associated with a product unit. The method may include: obtaining a plurality of data sets, wherein each of the plurality of data sets includes data associated with a spatial distribution of a parameter across the product unit; representing each of the plurality of data sets as a multidimensional object; obtaining a convolutional neural network model trained with previously obtained multidimensional objects and properties of previous product units; and applying the convolutional neural network model to the plurality of multidimensional objects representing the plurality of data sets, to predict the property associated with the product unit.

Abstract: A device is described having one or more conductive loops to produce an electromagnetic field, such as for wireless power transfer to an electronic device. In some examples, an antenna is used with at least one resonating capacitor ring that is relatively co-planar with the antenna, and that is magnetically coupled to the antenna but is not electrically powered by an external source. In addition, a device is described having two or more thin-film coils, each coil comprising a pair of terminals and at least one loop defining a plane and an interior region. In some examples, the planes of the two or more coils are disposed substantially parallel to one another, the interior regions of the two or more coils at least partially overlap one another, and the pairs of terminals of the antennae are electrically connected in parallel.

Abstract: A process mimicking forward modeler with deposition and erosion at each specific geological time step. The 3D derived properties are high resolution depositional environments and rock properties that are used to generate multiscale labelled synthetic data. These synthetic data can range from 1D logs such as grain size, gamma ray, density, and velocity, to 3D synthetic seismic, and are used directly as training data for various AIML applications.

Abstract: A power supply system of the embodiment includes a fuel cell which is able to generate power, a power storage device which stores the power generated by the fuel cell, a converter which converts power from the fuel cell or the power storage device and switches between supply of power from the fuel cell to an auxiliary device and supply of power from the power storage device to the auxiliary device, and a controller which controls at least the switching of the converter.

Abstract: Machine assisted systems and methods for enhancing the resolution of an IC thermal profile from a system analysis are described. These systems and methods can use a neural network based predictor, that has been trained to determine a temperature rise across an entire IC. The training of the predictor can include generating a representation of two or more templates identifying different portions of an integrated circuit (IC), each template associated with location parameters to position the template in the IC; performing thermal simulations for each respective template of the IC, each thermal simulation determining an output based on a power pattern of tiles of the respective template, the output indicating a change in temperature of a center tile of the respective template relative to a base temperature of the integrated circuit; and training a neural network.

Abstract: A Register Transfer Level (RTL) representation is recovered from a netlist representing an integrated circuit (IC). The netlist is converted to a graph comprising nodes belonging to a set of node types and edges connecting the nodes. The set of node types includes an instance node type representing an electronic component and a wire node type representing signal transfer between components. The graph is converted to a standardized graph by replacing subgraphs of the graph with standardized subgraphs. An RTL representation of the standardized graph is generated by operations including building signal declarations in a hardware description language (HDL) from the wire nodes of the standardized graph and building signal assignments in the HDL from instance nodes of the standardized graph.

Abstract: Security measures for signal paths with tree structures can be implemented at design phase using an EDA software program or tool with security feature functionality that, when executed by a computing system, directs the computing system to: display a canvas through which components of a circuit are arranged; and provide a menu of commands, including an option to add components from a library to the canvas and an option to secure a tree. In response to receiving a selection of the option to secure the tree, the system can be directed to add a hardware countermeasure coupled to at least two lines or terminal nodes of a tree structure identified from components on the canvas or in a netlist corresponding to a circuit's design.