Abstract: A chip package used as a logic drive, includes: multiple semiconductor chips, a polymer layer horizontally between the semiconductor chips; multiple metal layers over the semiconductor chips and polymer layer, wherein the metal layers are connected to the semiconductor chips and extend across edges of the semiconductor chips, wherein one of the metal layers has a thickness between 0.5 and 5 micrometers and a trace width between 0.5 and 5 micrometers; multiple dielectric layers each between neighboring two of the metal layers and over the semiconductor chips and polymer layer, wherein the dielectric layers extend across the edges of the semiconductor chips, wherein one of the dielectric layers has a thickness between 0.5 and 5 micrometers; and multiple metal bumps on a top one of the metal layers, wherein one of the semiconductor chips is a FPGA IC chip, and another one of the semiconductor chips is a NVMIC chip.

Abstract: An appropriate upper limit voltage is set to enable maximum charging performance of a secondary battery to be exhibited while effectively suppressing degradation of the secondary battery. An assembled battery control unit determines an upper limit voltage during charge of the secondary battery and calculates chargeable power of the secondary battery based on the upper limit voltage. The assembled battery control unit has an upper limit voltage calculating unit which calculates a voltage history of the secondary battery based on time series data of a voltage of the secondary battery and which calculates the upper limit voltage based on the voltage history.

Abstract: An approach is disclosed herein to sequence selection in a UVM environment. Generally, this approach includes a training phase for each machine learning model of a plurality of machine learning models. Each model is trained to achieve a particular target state and is rewarded when a selected action or sequence of actions causes movement that might be beneficial to achieving that target state. Once a respective model is trained, the trained model can then be used to determine which one action or sequence of actions (or ordered multiple thereof) to take to achieve the corresponding target state. Thus, by training and using a plurality of machine learning models to achieve a plurality of target states, and stimulating those machine learning models once trained, one or more actions and/or sequences of actions are generated as the selected sequences to be used to verify functionality or operation of a design under test.

Abstract: A layout method and apparatus based on a genetic algorithm are provided. The method includes: determining a gene code mode based on standard part information and layout part information; generating an initial population based on the gene code mode, the initial population including a plurality of gene codes, and the gene codes including standard code segments and layout code segments, and corresponding to layout schemes of standard parts and layout parts; acquiring fitness of each gene code; determining a dominant gene code based on the fitness; performing a double-point crossing operation and a double-point mutation operation on the dominant gene code to generate a next generation gene code, so as to form a dominant population; and if a preset termination condition is met, determining the layout scheme corresponding to the dominant gene code in the dominant population as a target layout scheme.

Abstract: A method and system for generating a clock distribution circuit for each macro circuit in an ASIC design are disclosed herein. In some embodiments, a method for generating a clock distribution circuit receives the ASIC design specified in a hardware description language (HDL), places each macro circuit in allocated locations on a semiconductor substrate, generates a custom clock skew information for each macro circuit based on a macro clock delay model, generates a clock distribution circuit for each macro circuit placed on the semiconductor substrate based on the generated custom clock skew information, modifies the clock distribution circuit if the generated clock distribution circuit does not meet timing requirements of the ASIC design, and outputs a physical layout of the ASIC design for manufacturing under a semiconductor fabrication process.

Abstract: Techniques are presented for the application of neural networks to the fabrication of integrated circuits and electronic devices, where example are given for the fabrication of non-volatile memory circuits and the mounting of circuit components on the printed circuit board of a solid state drive (SSD). The techniques include the generation of high precision masks suitable for analyzing electron microscope images of feature of integrated circuits and of handling the training of the neural network when the available training data set is sparse through use of a generative adversary network (GAN).

Abstract: Methods, systems and apparatus for generating plunge schedules for implementing iSWAP quantum logic gates between a first qubit and a second qubit. In one aspect, a plunge schedule that defines a trajectory of a detuning between a frequency of the first qubit and a frequency of the second qubit includes, during a first stage, non-adiabatically driving detuning between the frequency of the first qubit and the frequency of the second qubit through a first avoided crossing in a leakage channel, during a second stage, driving detuning between the frequency of the first qubit and the frequency of the second qubit through a second avoided crossing in a swap channel. during a third stage, allowing the first qubit and the second qubit to freely evolve and interact, during a fourth stage, implementing the second stage in reverse order, and during a fifth stage, implementing the first stage in reverse order.

Abstract: Techniques regarding parameter tuning for an EDA protocol are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise a tuning component that tunes an electronic design automation protocol via a cooperative co-evolutionary optimization framework that shares parameter knowledge across multiple stages of the electronic design automation protocol.

Abstract: Various embodiments of a method and apparatus for determining parametric timing yield and bottlenecks are disclosed which take into account correlation between electrical circuit paths through common timing arcs of an integrated circuit chip under design. Monte Carlo samples of timing arc delays are generated and used in computing timing yield and identify yield bottlenecks.

Abstract: Embodiments of the invention provide a power supply control method and a monitor system capable of executing the power supply control method. The monitor system includes a base station, an image capture apparatus, and a processor. The base station includes a charging apparatus including a power supply connector and a power source coupled to the power supply connector and outputting power through the power supply connector. The image capture apparatus shoots the power supply connector to obtain a shot image. The processor determines a foreign object distribution on the power supply connector according to the shot image and sends a warning message according to the foreign object distribution. The foreign object distribution relates to foreign objects formed on the power supply connector. Accordingly, whether a charging mechanism fails can be automatically determined and notification and/or compensation may be performed when the charging mechanism fails.

Abstract: Wirelessly charging a vehicle battery may be performed using a plurality of charging coils. In some examples, the offboard coils and the onboard coils may be spaced apart by different amounts, such that, when the vehicle is positioned in a vehicle charging space, at least one pair of an onboard coil and an offboard coil may still be substantially aligned for wireless charging, even when other coils are misaligned. In some examples, the offboard coils may include sizes that are conducive to charge smaller capacity systems in some arrangements and are combinable to charge larger capacity systems in other arrangements. In addition, the use of relatively small coils may allow for flexibility in thermal management.

Abstract: A quantum gate device includes a first superconducting circuit which resonates at a first resonance frequency, second superconducting circuit which resonates at a second resonance frequency, and connector which connects these circuits. The first superconducting circuit includes a single first Josephson device, second Josephson device group, and first capacitor. The second Josephson device group includes n Josephson devices connected by a line made of a superconductor. The Josephson energy possessed by each of the n Josephson devices is greater than n times that of the first Josephson device.

Abstract: With respect to each layout pattern of a plurality of layout patterns included in a layout for semiconductor processes, where the layout includes schematic information to form process patterns of a semiconductor device, vertical features indicating an effect of a lower structure on the process patterns are determined, and the lower structure indicates a structure that is formed in the semiconductor device before the process patterns are formed. A machine learning module is trained based on a training layout and the vertical features of the training layout. A design layout with schematic information to form target process patterns is corrected based on the trained machine learning module, the design layout and the vertical features of the design layout. Reliability and integration of the layout for the semiconductor processes may be increased by correcting the layout based on the vertical features and the horizontal features.

Abstract: A method for generating a reliability performance model includes developing a reliability prediction machine learning model for predicting reliability performance of a product based on data obtained from manufacturing and testing of the product, and obtaining feature names for the reliability prediction machine learning model and their predictive power values. The feature names may correspond to features from the data obtained from manufacturing and testing of the product. The method may further include extracting a set of feature names corresponding to features having highest predictive power values from the feature names, and generating a reliability performance model using one or more model parameters derived from the set of feature names.

Abstract: On-the-fly multi-bit flip-flop (MBFF) generation is provided by selecting at least two flip-flop blocks from a plurality of candidate flip-flop blocks; identifying a control block from a plurality of candidate control blocks, the control block being identified based on operational specifications of the selected flip-flop blocks; and generating a multi-bit flip-flop instance based on the selected flip-flop blocks and the identified control block.

Abstract: Methods and systems for performing post clock tree synthesis (CTS) of a clock tree include accessing, from memory, an integrated circuit design comprising a clock tree interconnecting a clock source to a plurality of clock sinks. Each clock sink has an associated current insertion delay. A mean insertion delay of the plurality of clock sinks is determined based on the associated current insertion delays of the clock sinks. A target insertion delay for the clock sinks is set based on the mean insertion delay and a target insertion delay adjustment determined for each individual clock sink. One or more clock sinks are identified that have a target insertion delay adjustment exceeding a skew threshold value. The clock tree is modified to reduce the target insertion delay adjustment, for each identified clock sink of the one or more clock sinks, to less than or equal to the skew threshold value.

Abstract: This application provides a charging pad used in a wireless charger. The charging pad can be wound. Specifically, the charging pad includes a rigid region and a flexible region, and a structure of the rigid region is different from a structure of the flexible region. A rigid support plate is disposed in the rigid region, and a metal line in the flexible region is in a metal hinge structure or is a bendable metal conducting wire. In addition, this application further provides a wireless charger to which the charging pad is applied.

Abstract: A hardware monitor arranged to detect livelock in a hardware design for an integrated circuit. The hardware monitor includes monitor and detection logic configured to detect when a particular state has occurred in an instantiation of the hardware design; and assertion evaluation logic configured to periodically evaluate one or more assertions that assert a formal property related to reoccurrence of the particular state in the instantiation of the hardware design to detect whether the instantiation of the hardware design is in a livelock comprising the predetermined state. The hardware monitor may be used by a formal verification tool to exhaustively verify that the instantiation of the hardware design cannot enter a livelock comprising the predetermined state.

Abstract: A liquid-cooled charging system for a vehicle is configured to dissipate heat generated during charging (including fast-charging) of an electrically-powered vehicle. The liquid-cooled charging system includes a charging assembly having an interface assembly configured to support a charging plug of a charging station and an energy transfer assembly configured to electrically couple the charging station to the battery of the vehicle during charging. Components of the charging assembly and energy transfer assembly also define a fluid circuit. A coolant system of the liquid-cooled charging system is fluidly connected to the fluid circuit, allowing coolant to flow through the fluid circuit to dissipate heat from the charging assembly components during charging of the vehicle.

Abstract: The present disclosure is directed to methods for generating a multichip, hybrid node stacked package designs from single chip designs using artificial intelligence techniques, such as machine learning. The methods disclosed herein can facilitate heterogenous integration using advanced packaging technologies, enlarge design for manufacturability of single chip designs, and/or reduce cost to manufacture and/or size of systems provided by single chip designs. An exemplary method includes receiving a single chip design for a single chip of a single process node, wherein the single chip design has design specifications and generating a multichip, hybrid node design from the single chip design by disassembling the single chip design into chiplets having different functions and different process nodes based on the design specifications and integrating the chiplets into a stacked chip package structure.