Abstract: Multi-cell battery management devices, systems, and methods are disclosed herein. A multi-cell battery management device comprises a battery pack including a power output terminal and a plurality of battery cells each having a positive and a negative terminal and connected in series fashion. Each of the plurality of battery cells includes: i) a cell control processor to monitor cell voltage, cell current, cell temperature, and cell fuse status; ii) a programmable shunt controlled by the cell control processor that varies the internal resistance of each of the cells; and iii) a data communications circuit connected to the cell control processor and to the positive and negative terminals of each cell, the communications circuit enabling data communication over the battery cell positive and negative output terminals, and wherein the cell control processor responds to commands received via the data communications circuit to vary the operating state of the programmable shunt.

Abstract: Systems and methods are disclosed for generation and testing of integrated circuit designs with point-to-point connections between modules. These may allow for the rapid design and testing (e.g. silicon testing) of processors and SoCs. For example, type parameterization may be used to generate point-to-point connections in a flexible manner. For example, a point-to-point connection between the source module and the sink module that includes one or more named wires specified by bundle type may be automatically generated based on using the bundle type as a type parameterization input. For example, these system and methods may be used to rapidly connect a custom processor design, including one or more IP cores, to a standard input/output shell for a SoC design to facilitate rapid silicon testing of the custom processor design.

Abstract: The present disclosure provides a method and an apparatus for testing a semiconductor device. The method includes providing an active area in an integrated circuit design layout; grouping the active area into a first region and a second region; calculating a first self-heating temperature of the first region of the active area; calculating a second self-heating temperature of the second region of the active area; and determining an Electromigration (EM) evaluation based on the first self-heating temperature and the second self-heating temperature.

Abstract: A chip package used as a logic drive, includes: multiple semiconductor chips, a polymer layer horizontally between the semiconductor chips; multiple metal layers over the semiconductor chips and polymer layer, wherein the metal layers are connected to the semiconductor chips and extend across edges of the semiconductor chips, wherein one of the metal layers has a thickness between 0.5 and 5 micrometers and a trace width between 0.5 and 5 micrometers; multiple dielectric layers each between neighboring two of the metal layers and over the semiconductor chips and polymer layer, wherein the dielectric layers extend across the edges of the semiconductor chips, wherein one of the dielectric layers has a thickness between 0.5 and 5 micrometers; and multiple metal bumps on a top one of the metal layers, wherein one of the semiconductor chips is a FPGA IC chip, and another one of the semiconductor chips is a NVMIC chip.

Abstract: A learning device for performing a machine learning based on a learning model using data input to an input layer, includes: a calculation part configured to calculate a predetermined number of features, in which simulation data as a result of simulating semiconductor manufacturing processes by setting environmental information inside a process vessel in which the semiconductor manufacturing processes are performed and using a predetermined component provided in the process vessel as a variable, and XY coordinates parallel to a plane of a wafer are associated with each other; and an input part configured to input the calculated predetermined number of features to the input layer.

Abstract: The system includes a rail mountable to a wall, such as a wall along a hallway in a medical care environment. A cart movable along a floor adjacent to the wall is fitted with an anchor. The anchor is located at the rail, the anchor configured so that it releasably engages the rail, so that the cart can be secured to the rail when not in use. In at least some embodiments, a power source is located within the rail and a power coupler is provided on the cart which is adjacent to the power source in the rail and electrically coupled to the power source, for transmission of power from the power source in the rail to the cart, when of the anchor on the cart is attached to the rail. Thus, the cart is both anchored and recharged simultaneously in such embodiments.

Abstract: A chip package used as a logic drive, includes: multiple semiconductor chips, a polymer layer horizontally between the semiconductor chips; multiple metal layers over the semiconductor chips and polymer layer, wherein the metal layers are connected to the semiconductor chips and extend across edges of the semiconductor chips, wherein one of the metal layers has a thickness between 0.5 and 5 micrometers and a trace width between 0.5 and 5 micrometers; multiple dielectric layers each between neighboring two of the metal layers and over the semiconductor chips and polymer layer, wherein the dielectric layers extend across the edges of the semiconductor chips, wherein one of the dielectric layers has a thickness between 0.5 and 5 micrometers; and multiple metal bumps on a top one of the metal layers, wherein one of the semiconductor chips is a FPGA IC chip, and another one of the semiconductor chips is a NVMIC chip.

Abstract: Provided is an energy storage apparatus capable of appropriately controlling use of a silicon material in normal times and achieving long life, and a method of using the energy storage apparatus. One aspect of the present invention is an energy storage apparatus that includes an energy storage device and a measuring section for measuring an internal pressure change rate of the energy storage device, the energy storage device having a negative electrode that contains a carbon material and a silicon material. Another aspect of the present invention is a method of using the energy storage apparatus that includes performing discharge while the internal pressure change rate of the energy storage device is measured.

Abstract: The present invention concerns a method and a tool for designing and validating a data flow system comprising a set of software and/or hardware actors (ai, aj) interconnected with each other by unidirectional communication channels (ci, cj), the tool comprising: —a modelling interface (11) configured to generate an instance of the system by specifying, in a formal manner, a real-time and reconfigurable data flow, the reconfiguration of the data flow being carried out dynamically by propagating reconfiguration data from one actor to another through the communication channels, —an analysis module (13) configured to prove a predetermined set of behavioral properties of the system by means of a static analysis of the instance, —a refinement interface (15) designed to allocate resources to the instance, thus establishing a configured instance, the allocation of resources being carried out in such a way that an implementation of the system complies with the configured instance, and —a conformity test module (17) co

Abstract: A method and apparatus for automatically generating periodic boiler combustion models and aperiodic boiler combustion models through automatic learning are provided. The method of automatically generating a boiler combustion model may include determining whether a specific event has occurred in association with a boiler, changing a training condition according to a result of the determining, generating a boiler combustion model trained on operation data measured in the boiler and stored in a database according to the training condition, and determining a precision of the generated boiler combustion model.

Abstract: Methods, machine readable media and systems for performing side channel analysis are described. In one embodiment, a method can determine, from a gate level representation of a circuit in a layout on a die of an IC, a first set of paths through the circuit that process security related data during operation of the circuit, the circuit including a second set of paths that do not process security related data; and the method can further determine, in a simulation of power consumption in the first set of paths but not the second set of paths, power consumption values in the first set of paths to determine potential security leakage of the security related data in the circuit. The method can further determine, from the power consumption values, positions in the layout for inserting virtual probes on the die for use in measuring security metrics that indicate potential leakage of the security related data. The insertion of the virtual probes is relative to the actual simulated layout of the die.

Abstract: An excitation source planning method for an electrical stimulation is proposed to plan an excitation source. A layout importing step is performed to drive a processing unit to import a PCB layout to an electromagnetic simulation software module. A port establishing step is performed to set the excitation source to be vertically disposed between a signal layer and a main ground layer. A model generating step is performed to perform the electrical simulation according to the excitation source to generate a three-dimensional simulation model corresponding to the PCB layout. When the signal layer is not electrically connected to the main ground layer, the electromagnetic simulation software module executes an extending step. The extending step is performed to provide a first metal unit to be connected to the signal layer, and reset the excitation source to be vertically disposed between the first metal unit and the main ground layer.

Abstract: Methods, systems and apparatus for performing windowed quantum arithmetic. In one aspect, a method for performing a product addition operation includes: determining multiple entries of a lookup table, comprising, for each index in a first set of indices, multiplying the index value by a scalar for the product addition operation; for each index in a second set of indices, determining multiple address values, comprising extracting source register values corresponding to indices between i) the index in the second set of indices, and ii) the index in the second set of indices plus the predetermined window size; and adjusting values of a target quantum register based on the determined multiple entries of the lookup table and the determined multiple address values.

Abstract: The present disclosure describes structures and methods for a via structure for three-dimensional integrated circuit (IC) packaging. The via structure includes a middle portion that extends through a planar structure and a first end and a second end each connected to the middle portion and on a different side of the planar structure. One or more of the first end and the second end includes one or more of a plurality of vias and a pseudo metal layer.

Abstract: An electronic device includes a display, a conductive coil, a wireless charging circuit electrically connected to the conductive coil, a power management circuit, a battery; and a processor, wherein the processor may be configured to control the electronic device to: measure a current flowing from the power management circuit to the wireless charging circuit while power is transferred to an external device through the conductive coil, and adjust the power transferred to the external device through the conductive coil based on a part of a power amount preset in a signal requesting addition of power based on a value of the current being between a first threshold value and a second threshold value greater than the first threshold value.

Abstract: A true random metastable flip-flop (TRMFF) compiler generates an electrical architecture for a TRMFF chain. The compiler selects components for the TRMFF chain from a library of standard cells and logically connects these components in accordance with a primitive polynomial to generate the electrical architecture. The TRMFF chain provides a sequence of random numbers from one or more physical processes in accordance with the primitive polynomial. During operation, one or more microscopic phenomena inside and/or outside of the TRMFF chain can cause one or more low-level, statistically random entropy noise signals to be present within the TRMFF chain. The TRMFF chain advantageously utilizes the one or more low-level, statistically random entropy noise signals to provide the sequence of random numbers.

Abstract: There are provided a learning apparatus, a learning method, and a program that enable, by using one type of device data, learning of a plurality of models using different data formats. A learning data acquiring section (36) acquires first data that is first-type device data. A first learning section (42) performs learning of a first model (34(1)) in which an estimation using the first-type device data is executed by using the first data. A learning data generating section (40) generates second data that is second-type device data the format of which differs from the format of the first-type device data on the basis of the first data. A second learning section (44) performs learning of a second model (34(2)) in which an estimation using the second-type device data is executed by using the second data.

Abstract: The present disclosure provides a circuit for balancing voltages of battery packs to be connected in parallel, comprising: IN-side switches and OUT-side switches; a DC-DC converter with an IN terminal connected to the IN-side switches and an OUT terminal connected to the OUT-side switches; and a controller to operate an IN-side switch to connect a Vmax battery pack to the IN terminal, operate an OUT-side switch to connect a Vmin battery pack to the OUT terminal, and activate the DC-DC converter to transfer energy from the Vmin battery pack to the Vmin battery pack. The controller responds to an IN terminal voltage being sufficiently close to a voltage of a first battery pack by operating an IN-side switch to connect the first pack to the IN terminal, and responds to an OUT terminal voltage being sufficiently close to a voltage of a second battery pack by operating an OUT-side switch to connect the second battery pack to the OUT terminal.

Abstract: Methods, systems and apparatus for simulating quantum circuits including multiple quantum logic gates. In one aspect, a method includes the actions of representing the multiple quantum logic gates as functions of one or more classical Boolean variables that define a undirected graphical model with each classical Boolean variable representing a vertex in the model and each function of respective classical Boolean variables representing a clique between vertices corresponding to the respective classical Boolean variables; representing the probability of obtaining a particular output bit string from the quantum circuit as a first sum of products of the functions; and calculating the probability of obtaining the particular output bit string from the quantum circuit by directly evaluating the sum of products of the functions. The calculated partition function is used to (i) calibrate, (ii) validate, or (iii) benchmark quantum computing hardware implementing a quantum circuit.

Abstract: A security verification system performs security verification of a circuit design. The security verification system simplifies formal security verification of the circuit design by replacing circuit blocks of the circuit with black box circuit blocks. The security verification system instruments the circuit design so that black-boxing can be performed for security verification without changing the security decision over the data paths. The security verification system uses dependence information of the inputs and outputs of the black box to connect inputs of the circuit block with outputs of the circuit block. The black-box circuit block keeps the logic inside the cone of influence of clocks and resets. The system performs security verification of the circuit design by proving a non-interference property of the instrumented circuit design.