Abstract: A rigid wireless charging mouse pad includes a rigid board layer, a double-sided adhesive plate and a coil. The underside of the rigid board layer has a single-ring groove with an inner top groove wall. The double-sided adhesive plate is adhered to the inner top groove wall. The coil has surrounding rings arranged side by side with one another to form a coil module which is stacked on the double-sided adhesive plate in the single-ring groove and adhered by the double-sided adhesive plate to achieve a wireless charging effect by the mouse pad in the condition of having only one single-ring groove on the rigid board layer, so as to achieve the effects of reducing manufacturing difficulty, lowering manufacturing cost, and improving market competitiveness.

Abstract: Techniques are presented for the application of neural networks to the fabrication of integrated circuits and electronic devices, where example are given for the fabrication of non-volatile memory circuits and the mounting of circuit components on the printed circuit board of a solid state drive (SSD). The techniques include the generation of high precision masks suitable for analyzing electron microscope images of feature of integrated circuits and of handling the training of the neural network when the available training data set is sparse through use of a generative adversary network (GAN).

Abstract: A system for inductive power transfer includes a charger. The charger is an inductive charger. The system also includes a first mobile device that includes a receiver to inductively receive power for the first mobile device. A charger for inductive charging includes a printed circuit board having a charger coil, a substantially planar magnetic layer, a charger drive circuit, and means for positioning a receiver in a power transfer position. A mobile device that receives power inductively includes a receiver to inductively receive power for the mobile device. A method for inductive power transfer to a mobile device, which includes a receiver, includes positioning the receiver in a power transfer position to inductively receive power from an inductive charger. The method further includes inductively transferring power from the charger to the receiver of the first mobile device.

Abstract: While a qubit control system (e.g., a laser system) is in a first configuration, it causes a qubit state (as represented as a point on the surface of a Bloch sphere) of a quantum state carrier (QSC), e.g., an atom, to rotate in a first direction from an initial qubit state to a first configuration qubit state. While the qubit control system is in a second configuration, it causes the QSC state to rotate in a second direction opposite the first direction from the first configuration qubit state to a second configuration qubit state. The second configuration qubit state is read out as a |0 or |1. Repeating these actions results in a distribution of |0s and |1s that can be used to determine which of the two configurations results in higher Rabi frequencies. Iterating the above for other pairs of configurations can identify a configuration that delivers the most power to the QSC and thus yields the highest Rabi frequency.

Abstract: The external heterogeneity in the Discrete Event System Specification (DEVS) for simulators refers to the ability to incorporate different types of models, each with potentially different behaviors, into a single simulation environment. In the DEVS framework, a system is composed of multiple individual models, each representing a component of the system. These models can be either atomic (cannot be decomposed further) or coupled (composed of other models). This gives DEVS its hierarchical nature. The atomic or coupled models can in DEVS Markov models be fundamentally different from each other. For example, one model might represent a deterministic rule-based decision process, while another model might represent a probabilistic random variable generator. These models have different state variables, different event sets, and different transition functions, but they can still interact with each other within the same simulation.

Abstract: A method includes extracting information associated with constraints and clock information from a file of a circuit design; determining a topological cone based on the extracted information for a partition of two or more partitions of the circuit design, and performing timing analysis on the partition of the two or more partitions based on the topological cone. The topological cone includes objects associated with the partition of the two or more partitions of the circuit design.

Abstract: Techniques and systems for enhanced adjustment of quantities and placement of decoupling capacitance on circuit boards for integrated circuits is provided herein. An example method includes iterating application of a load profile across different populations of decoupling capacitors on a circuit board for supply voltage domains of an integrated circuit device until a target transient performance is reached for the supply voltage domains. The load profile is applied onto electrical connections corresponding to the supply voltage domains for the integrated circuit device. The method also includes generating a capacitor population configuration for the circuit board based on a population of the decoupling capacitors that achieves the target transient performance.

Abstract: Aspects of the subject disclosure may include, for example, obtaining instructions for implementing a quantum algorithm adapted to obtain a computational result according to a quantum mechanical process. A sequence of quantum operations is generated according to the instructions for implementing the quantum algorithm, wherein the sequence of quantum operations is adapted to physically manipulate a plurality of quantum bits according to the quantum mechanical process. The sequence of quantum operations is provided to a geographically separated quantum central module, via a communication channel, the geographically separated quantum central module implements the quantum mechanical process to obtain a computational result. The computational result is received from the geographically separated quantum central module via the communication channel. Other embodiments are disclosed.

Abstract: One embodiment provides an electrical circuit coupled to an alternator. The electrical circuit includes a rotor and stator coils. The electrical circuit is configured to receive, at a point when an engine is operating, an electrical current that is induced in the stator coils by rotation of the rotor and charge a battery pack with the electrical current and inhibit generation of a spark by the engine while the alternator is powered by the battery pack until a speed of the alternator is greater than a threshold. The electrical circuit is further configured to power the alternator, at a point when the engine is not operating, with electrical current supplied by the battery pack coupled to a battery connector to start the engine.

Abstract: A computing system configured to verify design of an integrated circuit (IC) includes a memory and a processor. The memory is configured to store computer executable instructions. The processor is configured to generate a first coverage model for at least two high-level parameters from the Institute of Electrical and Electronics Engineers (IEEE) 802.11 standard or hardware description language (HDL) code by executing the computer executable instructions, generate a second coverage model for low-level internal signals from the HDL code by executing the computer executable instructions, and generate a plurality of test packets for a regression test by using at least one of the first coverage model or the second coverage model by executing the computer executable instructions.

Abstract: A system and method is described herein for data filtering to reduce functional, and trend line outlier bias. Outliers are removed from the data set through an objective statistical method. Bias is determined based on absolute, relative error, or both. Error values are computed from the data, model coefficients, or trend line calculations. Outlier data records are removed when the error values are greater than or equal to the user-supplied criteria. For optimization methods or other iterative calculations, the removed data are re-applied each iteration to the model computing new results. Using model values for the complete dataset, new error values are computed and the outlier bias reduction procedure is re-applied. Overall error is minimized for model coefficients and outlier removed data in an iterative fashion until user defined error improvement limits are reached. The filtered data may be used for validation, outlier bias reduction and data quality operations.

Abstract: A comparative rejection sampling technique selects a bound set of possible execution run results for a process to be simulated, such as a quantum circuit, for each possible execution run result a modeled probability of a state associated with the possible execution run result is determined. For example a tensor network algorithm may be used to determine quantum state probabilities for each quantum state execution result included in the bound set. Based on the determined probabilities one of the possible execution run results is selected from the set of possible execution run results as an accepted simulated execution run result for a run of the process being simulated.

Abstract: The present disclosure provides a method for evaluating a heat sensitive structure. The method includes identifying a heat sensitive structure in an integrated circuit design layout and identifying a heat generating structure in the integrated circuit design layout. The method also includes calculating an operating temperature of the heat generating structure by taking a practical current distribution into consideration. The method also includes calculating an anticipated temperature increase for the heat sensitive structure induced by thermal coupling of the heat generating structure at the operating temperature.

Abstract: A method of reinforcement learning of a neural network device for generating a verification vector for verifying a circuit design comprising a circuit block includes inputting a test vector to the circuit block, generating one or more rewards based on a coverage corresponding to the test vector, the coverage being determined based on a state transition of the circuit block based on the test vector, and applying the one or more rewards to a reinforcement learning.

Abstract: A quantum computer directs an amplitude of a qubit to be proportional to the value of a function g of N variables {right arrow over (xk)} by: (A) initializing M+1 qubits on the quantum computer, the M+1 qubits comprising: (1) a target qubit t having an amplitude of a reference state; and (2) a control register with M qubits {ql}; and (B) changing the value of the amplitude of the reference state on the target qubit t, the changing comprising: (B)(1) applying a sequence of SU(2) gates to the target qubit t, the sequence of SU(2) gates comprising M controlled quantum gates Gi and at least one rotation parameter, wherein at least one qubit of the control register acts as a control qubit for the controlled quantum gate Gi; and (B)(2) tuning the at least one rotation parameter until a halting criterion based on the amplitude of the reference state is satisfied.

Abstract: Machine assisted systems and methods for enhancing the resolution of an IC thermal profile from a system analysis are described. These systems and methods can use a neural network based predictor, that has been trained to determine a temperature rise across an entire IC. The training of the predictor can include generating a representation of two or more templates identifying different portions of an integrated circuit (IC), each template associated with location parameters to position the template in the IC; performing thermal simulations for each respective template of the IC, each thermal simulation determining an output based on a power pattern of tiles of the respective template, the output indicating a change in temperature of a center tile of the respective template relative to a base temperature of the integrated circuit; and training a neural network.

Abstract: The present disclosure provides a method and a system for determining the equivalence of the DRM data set and the DRC data set. The system retrieves a DRM data set and a DRC data set, and transforms the DRM data set and the DRC data set into a first data structure node and a second data structure node respectively. The system determines whether the first data structure node and the second data structure node are equivalent according to a data structure node comparison model.

Abstract: A method for manufacturing a lithographic mask for an integrated circuit includes performing an optical proximity correction (OPC) process to an integrated circuit mask layout to produce a corrected mask layout. The method further includes performing an inverse lithographic technology (ILT) process to the corrected mask layout to enhance the corrected mask layout to produce an OPC-ILT-enhanced mask layout. The method also includes performing an inverse lithographic technology (ILT) process to the corrected mask layout to enhance the corrected mask layout to produce an OPC-ILT-enhanced mask layout.

Abstract: A system and method for characterizing a memory instance. Characterizing a memory instance includes obtaining a memory instance comprising a plurality of leaf cells. Each of the plurality of leaf cells comprises components. First channel connected components from the components within each of the plurality of leaf cells are determined, and a first super leaf cell is generated by combining a first two or more leaf cells of the plurality of leaf cells based on the first channel connected components. Further, an updated memory instance is generated based on the first super leaf cell, and a timing model is determined for the updated memory instance.

Abstract: Various aspects of the present disclosed technology relate to techniques for classifying layout patterns. First, a set of density feature vectors for a set of layout regions in the layout design are extracted using a set of rings. Each component of a density feature vector in the set of density feature vectors corresponds to a ring in the set of rings. The set of rings do not overlap with each other and cover a whole area of a circle when being placed together. Next, a machine learning-based clustering process is performed to separate layout features in the set of layout regions into clusters of layout features based on the set of density feature vectors. Each of the clusters of layout features may be further divided into subclusters based on one or more properties.