Abstract: Systems and devices are provided to enable granular control over a retention or active state of each of a plurality of memory circuits, such as a plurality of memory cell arrays, within a memory. Each respective memory array of the plurality of memory arrays is coupled to a respective ballast driver and a respective active memory signal switch for the respective memory array. One or more voltage regulators are coupled to a ballast driver gate node and to a bias node of at least one of the respective memory arrays. In operation, the respective active memory signal switch for a respective memory array causes the respective memory array to transition between an active state for the respective memory array and a retention state for the respective memory array.

Abstract: A system for configuring a handheld device based on a state of the handheld device includes an embedded controller (EC), a provided service, user selectable thermal tables (USTT), an Operating System (OS) scheduler, a power plan management (PPM) service and a thermal management service (TMS). The provided service communicates with the EC to determine if the handheld device is docked or coupled to a power supply, is stationary or moving, is coupled to an external display and whether a Peak Mode button is activated and communicates signals to one or more of the USTT, the OS scheduler, the PPM and the TMS to configure the handheld device in one of an Ultra Performance Mode, an Optimized Mode, a Quiet Mode or a Peak Mode.

Abstract: Hierarchical power estimation and throttling in a processor-based system in an integrated circuit (IC) chip, and related power management and power throttling methods are disclosed. The IC chip includes a processor as well integrated supporting processing devices for the processor. The hierarchical power management system controls power consumption of devices in the IC chip to achieve the desired performance in the processor-based system based on activity power events generated from local activity monitoring of devices in the IC chip. The hierarchical power management system includes a centralized power estimation and limiting (PEL) circuit that is configured to track and merge received power throttle recommendations associated with related activity power events for monitored processing devices to generate one or more power limiting management responses to throttle power consumption of related devices that may be contributing to excess power consumption.