Patents Examined by Byran Junge
  • Patent number: 8765572
    Abstract: A method of fabricating a semiconductor device, in which an interference effect between word lines is substantially reduced or eliminated, includes forming a plurality of gate patterns on a substrate; forming a first insulating layer between the gate patterns, the first insulating layer filling a region between the gate patterns; etching the first insulating layer to remove a portion of the first insulating layer to a predetermined depth; and forming a second insulating layer on the gate patterns and the first insulating layer. A low-dielectric-constant material is formed between the gate patterns.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: July 1, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-lack Choi, Chang-hyun Cho, Seung-pil Chung, Hyun-seok Jang, Du-heon Song, Jung-dal Choi