Abstract: Disclosed is a method of fabricating a stoichiometric gallium oxide (Ga.sub.2 O.sub.3) thin film with dielectric properties on at least a portion of a semiconducting, insulating or metallic substrate. The method comprises electron-beam evaporation of single crystal, high purity Gd.sub.3 Ga.sub.5 O.sub.12 complex compound combining relatively ionic oxide, such as Gd.sub.2 O.sub.3, with the more covalent oxide Ga.sub.2 O.sub.3 such as to deposit a uniform, homogeneous, dense Ga.sub.2 O.sub.3 thin film with dielectric properties on a variety of said substrates, the semiconducting substrates including III-V and II-VI compound semiconductors.

Abstract: A photo-assisted chemical vapor deposition system includes a reaction chamber, a susceptor in the reaction chamber supporting a wafer, a source for introducing reactant gas into the reaction chamber through an inlet port, and a cover positioned in sealed relationship to the housing and partially bounding the reaction chamber, the cover including a plurality of elongated light pipe openings each having a length comparable to the thickness of a boundary layer of the reactant gas and a diameter-to-length ratio small enough to maintain one-dimensional purge gas flow through the light pipe openings. A plurality of transparent windows are disposed in sealed relationship with the cover and bound an outer end of each of the light pipe openings. Ultraviolet light is introduced through the light pipe openings, which also provide a thick gas layer through which reactant species of the reactant gas must diffuse to reach the window surface.

Abstract: In an improved selection tungsten metallization system, a plurality of orifices (20) are cut into a first level dielectric layer (18). A nucleation layer (52), preferably Ti-W alloy, is then formed in each orifice (20) and on the outer surface of the first dielectric layer (18) in a second-level metallization pattern. A second dielectric layer (30) is deposited over the first dielectric layer (18) and the nucleation layer (52), and a reverse second level metallization pattern is used to etch slots (58) back down to the nucleation layers (52) and into orifices (20). Thereafter, tungsten is deposited by selective CVD to fill the first level orifices (20) and the second level slots (58) until the upper surfaces (62) of the tungsten conductors (60) are substantially coplanar with the upper surface (38) of the second dielectric layer (30).

Abstract: A three-layer metal contact including aluminum is provided for silicon-based semiconductor devices to minimize the effects of formation of silicon precipitates in the aluminum layer and low contact junction leakage. The metal contact comprises a first layer of a refractory metal silicide formed on a silicon surface, an intermediate layer of aluminum formed on the refractory metal silicide and a top layer of a refractory metal silicide formed on the layer of aluminum. Where contact is made to polysilicon layers forming high resistance load resistors, the metal contact of the invention prevents reduction in resistance resulting from the interdiffusion of silicon and aluminum.

Abstract: A cost effective method of fabricating a large array or pagewidth silicon device having high resolution is disclosed. The pagewidth device is assembled by abutting silicon device sub-units such as image sensors or thermal ink jet printheads. For printheads, the sub-units are fully operational small printheads comprising an ink flow directing channel plate and a heating element plate which are bonded together. A plurality of individual printhead sub-units are obtained by dicing aligned and bonded channel wafers and heating element wafers. The abutting edges of the printhead sub-units are diced in such a manner that the resulting kerfs have vertical to inwardly directed sides which enable high tolerance linear abutment of adjacent sub-units. Alternatively, the wafer surface containing the heating elements is first anisotropically etched to form small V-grooves, one wall of which protects against microcracking during the dicing operation. The other wall of the V-groove is obliterated by the slanted dicing blade.

Abstract: A method for separating chips formed on a silicon substrate is provided which uses a combination of reactive ion etching techniques combined with orientation etching to yield integrated chips having edges which can be more precisely butted together to form large area arrays.

Abstract: A method is provided for the oxidation of a silicon or gallium arsenide surface by depositing thereon a samarium or ytterbium overlayer prior to exposure of the surface to an oxidizing atmosphere.