Abstract: Plural scan test paths (401) are provided to reduce power consumed during testing such as combinational logic (101). A state machine (408) operates according to plural shift states (500) to control each scan path in capturing data from response outputs of the combinational logic and then shifting one scan path at a time to reduce the capacitive and constant state power consumed by shifting the scan paths.

Abstract: A structure and method for an integrated circuit which includes read/write memory having a plurality of memory devices, each of the memory devices having a unique address; a built-in self-test (BIST) engine, the BIST engine having a controller responsive to a test enable signal and operative to generate and store test data in the read/write memory; a comparator operative to compare retrieved data read from the read/write memory and the test data during a first pass test, the comparator identifying failed cycles where the retrieved data does not correspond correctly to the test data; and a diagnostic unit operative to store the failed cycles and being responsive to the controller generating and storing the test data in the read/write memory and operative to store failed data and failing addresses during a first pass test, wherein the BIST engine stops only at each of the failed cycles during the first pass test.

Abstract: A financial document processing system for processing financial documents is operated to assist an operator during exception recovery. During exception recovery, an original codeline, an encoded data string, and a recovery codeline associated with a financial document are obtained. Any blank spaces from the original codeline, the encoded data string, and the recovery codeline are stripped to provide a stripped original codeline, a stripped encoded data string, and a stripped recovery codeline, respectively. A number of characters of the stripped recovery codeline and a number of characters of the stripped original codeline are compared to determine if there is a match between the original codeline and the recovery codeline.

Abstract: A method for writing data to a mass data storage device (10) includes applying a maximum transition run length code constraint to the data to be written, generating parity data based on the data, and inserting the parity data into the data to be written (5A-C). The parity data is used in conjunction with a post-processor (66) to detect and correct errors in the read back data.

Abstract: A multi-bit-per-cell memory reduces the effect of defects and data errors by scrambling data bits before writing data. The scrambling prevents storage of consecutive bits in the same memory cell. When a memory cell is defective or produces an error, the bits read from the memory cell do not create consecutive bit errors that would be noticeable or uncorrectable. An error or a defect in a multi-bit memory cell causes at most scattered bit errors. Scramblers in multi-bit-per-cell memories can include 1) hardwired lines crossing between an input port and an output port, 2) programmable wiring options, 3) a linear buffer where reads from the buffer use addresses with swapped bits, or 4) a buffer array that switches between incrementing a row address first and incrementing a column address first when accessing memory cells in the buffer array.