Abstract: A power and free conveyor transfer system includes a number of drive trolleys operating within a free track and being selectively propelled by endless drive chains within a vertically aligned power track. Each drive trolley includes a trolley housing body to which are rigidly attached a pair of downwardly extending lateral arms, each with a rearward facing drive surface. A pivotable drive member is attached to the front end of the trolley housing and extends backward and downward between the lateral arms with a drive dog forming a portion thereof. The drive trolley design facilitates transfer of each drive trolley between non-synchronous delivering and receiving power tracks in a conveyor transfer zone. Within the transfer zone, the delivering and receiving power tracks are at different elevations and approach each other from a relatively large angle to minimize the potential for mechanical interference or jamming.

Abstract: A hydraulic tensioning device for tensioning the rigging of a sailing vessel comprises first, second and third components which are telescopical with respect to one another. A cylinder of the first component and a piston of the second component form a first chamber, and a cylinder of the second component and a piston of the third component form a second chamber, the two chambers being in fluid flow communication with one another via a passage. The first component is connected to one part of the rigging, and the second component to another part of the rigging. The rigging is tensioned by applying tension to a rope or wire connected to the third component. In another embodiment the first component is mounted for guided displacement along a rail, the second and third components each being connected by a rope or wire to a cam cleat to limit longitudinal displacement.

Abstract: A microcomputer having a microprocessor operative in response to a dual frequency clock, such microprocessor being adapted to read data stored in a programmable memory in response to address and read enable signals supplied to a programmable memory and being adapted to process such data in response to the clock pulses supplied by the dual frequency clock. The dual frequency clock produces clock pulses at a relatively low rate until such time as either a sensing device is activated or a time duration has passed, in which case the mine is to selfdestruct. When the sensor is activated the microprocessor commands the dual frequency clock to produce relatively high frequency clock pulses to enable the microprocessor to rapidly determine whether the mine should or should not be detonated. Relatively low power is consumed by the microcomputer during the period of time the processor is "counting time" and computing whether the predetermined period of time has arrived, i.e.

Abstract: An information processor functions to continuously and successively read out from an external memory a plurality of records each consisting of a plurality of words, extract a record whose specified word used as a key word corresponds to the designated condition and store the record in a main memory and is characterized in that it comprises an address memory for successively writing each record in the main memory and receiving and storing an address data each time the heading address of each record is written in and a means for returning the address of the main memory to the heading address stored in the address memory when the result of the collation between the designated key word of the record written in the main memory and a prescribed condition proves that the key word does not correspond to the condition.

Abstract: A data transfer system receives incoming digital data serially at a predetermined bit rate and transfers such data serially at a different bit rate. A distributing device distributes the bits of incoming data into a plurality of groups. A delay device connected to the distributing device delays the bits of each group by predetermined delay times. An assembly device connected to the distributing device and the delay device assembles the delayed bits of each group into a group having a bit rate different from that of the incoming data.

Abstract: In order to incorporate a very high speed memory subsystem into a computer system utilizing unified bus architecture, memory control apparatus associated with the very high speed memory is provided with a first port communicating directly with a system central processor and a second port interfacing with the unified bus. The memory control apparatus may include means for systematically refreshing volatile high speed memories. Multiple processor systems may be realized by taking advantage of the dual port characteristics of the very high speed memory subsystems associated with each central processor.

Abstract: A central processor for controlling the operation of the subsystems of a telephone exchange switching system which are interconnected on a common data bus to establish requested service between telephone subscribers, wherein the exchange system includes a program memory also connected to the common data bus for storing a plurality of selectable multiple bit operational codes to be utilized by the central processor in response to a particular service being requested, a program address register for selecting a desired operational code from the program memory, an instruction register for storing the selected operational codes and a control word generator which provides function control signals in response to the particular operational codes stored in the instruction register. A bit time counter coupled to the control word generator controls the timing of the central processor so that the function control signals are supplied in proper time sequence.