Abstract: An image-forming apparatus which forms an image in an oblique print mode in units of blocks which are separated by line spaces. Every time the count value of the white-dot counter 96 reaches the predetermined value, it is determined that an image block is spaced apart from the preceding one. The data item representing the first line of the image block is not shifted at all, and the data items representing the following lines of the image block are shifted by the distance proportional to the angle, by twice said distance, by thrice said distance, and so on. As a result, the image data is printed on a paper sheet, in an oblique form, with no parts extending outside the paper sheet.

Abstract: A cache memory which includes a cache controller formed on a single substrate. A plurality of the memories may be used in an array. The memories themselves determine how many other memories are in an array and each of their relative positions in the array. From this information, each memory sets the range of its set fields and the size of its tag fields. This is done on reset with the configuration information being distributed among the memories themselves, without being centrally stored, and in a manner transparent to the software.

Abstract: A router circuit for selectively connecting an input terminal of the router circuit to either a specified output terminal of the router circuit (crossbar personality) or to any of a group of output terminals of the router circuit associated with a single output channel (hyperbar personality). The router circuit is made configurable as either a crossbar switch or a hyperbar switch by dividing the router chip into sections, where each section is associated with a group of input terminals, and wherein various grant circuits within each of the sections have enable/disable input terminals connected by controllable switches to either enable/disable output terminals of grant circuits in an adjacent section (hyperbar personality) or to fixed logic levels (crossbar personality). In the crossbar configuration, for each input terminal of a section, only one grant circuit per channel is enabled.

Abstract: An ISA-compatible computer system includes an additional function key on its keyboard. The additional function key does not have a defined function for conventional ISA-standard computers. When a conventional alphanumeric key or function key is activated on the keyboard, the computer system is interrupted using IRQ1 and the key information is communicated to the computer system so that the computer system can respond in a conventional manner using a conventional keyboard interrupt handling routine. When the additional function key and an alphanumeric key are activated in combination, a second interrupt different from the IRQ1 interrupt is activated (e.g., IRQ15). The computer system responds to the second interrupt by inputting an identification of the activated alphanumeric key and performing a selected predetermined function in response thereto.

Abstract: The I/O configuration of a computer system includes two channels which are capable of being available on up to four interface ports, with the ports being incorporated within the channel in order to eliminate the need for an external switch. Control means are provided for monitoring the status of each channel and each port in order to achieve expeditious transfers through a selected port between the channel and peripheral devices. Error reporting is limited to the area directly affected by the error, and immediate disconnection helps to isolate the error and allow time for error recovery before the particular channel or port again becomes available.

Abstract: Count, key, data (CKD) datas are stored on fixed block (FBA) disk recorders (DASD). A virtual track is created which emulates a physical CKD track such that the byte displacement of each CKD record on the virtual CKD track is the same as the byte displacement would be on a physical CKD track. This enables computer programs using CKD formatted data to record on the FBA recorder in an emulation mode. Each FBA block includes a header outside the addressing of the virtual CKD track which includes a byte displacement pointer to the beginning of a first CKD record stored in the FBA block, if any begins in such FBA block; otherwise the header indicates that no CKD record begins in the block. A last record indicator is included in the count field emula-tion for assisting in finding end of the virtual track.

Abstract: A flexible dynamic memory controller that is operable with dynamic RAMS having a wide range of operating characteristics. These characteristics include different operating speeds for various memory functions, and the usage of memories. In a state machine, a special register is utilized to control where in the sequence of operation, and for how long various delays must be inserted. The delays are dynamically determined by the memory controller in accordance with the type of memory being accessed at a given time and the source of the request.

Abstract: An intelligent power supply system for a portable computer, the computer having a central processing unit (CPU), and being operable in response to power supplied from at least two chargeable batteries or an alternating current (AC) adapter, includes means for detachably coupling the batteries to the computer and a PC-CPU for controlling power supply independent of the CPU. The PC-CPU has means for receiving battery select information for controlling power supply and generating a control signal. The power supply system further includes battery control circuit means, connected to the AC adapter and the batteries, for selecting and controlling the AC adapter or one of the batteries based on the control signal. Accordingly, the proper battery for the usage can be installed in the portable computer operable on battery power, and the computer can be operated continuously on the battery power for a long period of time.

Abstract: A computer-aided software engineering facility and method for creating computer source code and executable computer programs that are distributable across multiple hardware environments or platforms. An object oriented modeling system is linked with modules of a computer programming language and other system components to quickly and efficiently design computer source code and executable computer modules that have a high degree of reusability. The modules and models are stored in a centralized storage area and distributed to the various hardware elements that comprise the computer system.

Abstract: A digital signal processor with a built-in dual-port RAM and a bypass signal path for transferring data without the intervention of any bus which is extended between the two ports of the data RAM, whereby in the course of multiply-and-add processing necessary for filter processing, sampling data items to be read out of a predetermined address of the data RAM can be transmitted to an internal bus and can simultaneously be written into the next address of the data RAM to be shifted thereto, in one memory cycle of the data RAM.

Abstract: A peripheral adapter board and circuit which is capable for operation with two different personal computer bus architectures is disclosed. The preferred peripheral function for the board and circuit is a terminal emulator, which allows a personal computer into which the board is plugged to function as a terminal for a mainframe or minicomputer. Edge connectors or contacts are provided on opposite side edges of the board; each one of the edge connectors is compatible with a different computer bus. The adapter board may be flipped over to plug into either computer bus. A removable, repositionable connector board assembly is provided at one end of the board, for mounting communications connectors in a position accessible from the back panel of a host personal computer. The connector board may be repositioned to maintain the orientation of the communications connectors with respect to the personal computer back panel when the adapter board is flipped over to plug into a different computer bus.

Abstract: A priority selector of a system including a plurality of processors and a shared source commonly used by the processors sets a priority of requests supplied from the processors for using the shared source and supplies a use permission to a single processor. The priority selector has a plurality of lock request priority setting circuits corresponding to the processors and a request selector. When a contention occurs between an own request from a processor and other request from another processor, the corresponding lock request priority setting circuit upgrades the non-permitted own request as a high priority request when the other request is permitted, and downgrades a following own request as a low priority request when the own request is accepted.

Abstract: A hardware-based system for managing multiple input/output devices sharing the same set of addresses in a computer system is described. The new VIRTUAL ENABLED state is a hybrid of the current ENABLED or ACTIVE and DISABLED or INACTIVE states. In the ENABLED state, an input/output (I/O) adapter responds to I/O addressing and presents interrupts to the processor. In the DISABLED state, the I/O adapter does not respond to I/O addressing and does not present interrupts. In the new VIRTUAL ENABLED state, the adapter does not respond to I/O addressing (as in the DISABLED state), but will still produce an interrupt (as in the ENABLED state). With the VIRTUAL state, multiple I/O adapters that would normally content for the same set of addresses (ENABLED state), or optionally be rendered inoperable (DISABLED state), can always remain available for I/O. A single register where the processor can read the interrupt status for all ENABLED and/or VIRTUAL ENABLED adapters sharing the same set of addresses is provided.

Abstract: In an address multiplexing apparatus for multiplexing address data to be supplied to 64K bit, 256K bit, and 1M bit DRAMs, upon multiplexing of address data, input address data of 20 bits are classified into two groups, i.e., the lower 16 bits and the upper 4 bits. The lower 16-bit group is multiplexed so that the upper 8 bits serve as row address data, and the remaining lower 8 bits serve as column address data. In the upper 4-bit group, adjacent bits are multiplexed. The apparatus can be commonly used for the three memories having different capacities with the simple circuit arrangement, and page mode access can be executed.

Abstract: A system for multiplexed transfer of data between plural blocks interconnected by a two-way data bus of a predetermined number of bus lines provides for simultaneous and parallel transfer over the plural bus lines of plural data bits, up to the same, maximum predetermined number of the bus lines. Each parallel data bit transfer is selectively controllable with respect both to the number and the direction of transfer of the individual data bits over the respectively corresponding bus lines of the two-way data bus. Each block comprises a plurality of internal circuit cards, an internal bus of plural bus lines, of the same predetermined number, respectively connected to plural internal circuit cards of the block, and plural two-way transfer gates respectively associated with and selectively operable for interconnecting the corresponding bus lines of the internal bus and the two-way data bus.

Abstract: A ladder climbing safety clamp is claimed that may be easily operated by a worker with one hand while overcoming many potential safety hazards of prior devices. The safety clamp includes a body with a U-shaped cable sleeve. A channel is included on one side of the body to permit the introduction of the safety line in the cable sleeve. However, if the cable is too large to operate properly with the safety clamp, it will not fit through the channel, thereby helping to prevent inadvertent usage of the safety clamp with a cable of a diameter for which it is not intended. A gravity stop is also provided to prevent the safety clamp from being inadvertently installed in an upside-down position, since the safety clamp would not operate correctly in that position.

Abstract: A method for translating a virtual address into a physical address, in which page tables used in the translation process are referenced by virtual addresses. Typically, a translation mechanism includes a translation buffer that, given a virtual address, can sometimes provide the corresponding physical address. A translation-buffer miss is said to occur when the translation buffer is presented with an address for which it can not provide the translation. When such a miss occurs, the translation mechanism obtains the translation by reading the page tables. When the translation mechanism attempts to read the page tables from virtual memory, a second-order miss can occur. The difficulty of infinite recursion of misses is avoided by handling second-order misses differently from first-order misses. When a second-order miss occurs, the translation mechanism uses a prototype page table entry and the virtual address of the page table entry to produce a physical address without using the page tables.

Abstract: A control register residing in a circuit chip stores a set of hardware parameters which exercise programmable control over circuits in the chip to allow for various critical hardware options. A plurality of chips and their control registers may be addressed and written individually by a processor through normal bus access. Each control register is permitted to be written only once, shortly after reset. A circuit, in response to a reset signal and a chip select signal, enables the individual control register for writing, and further, in response to a write strobe, latches data from the data bus into the register and soon afterwards ceases enabling the register for further writes.

Abstract: In a desktop computer, a hard disk drive activity indicator such as an LED is mounted on the front panel, remote from its associated hard disk drive which is mounted in the back of the housing. The LED is triggered in response both I/O writes for addresses reserved for use with the hard disk, and interrupt requests generated by the hard disk drive. Triggering logic on the motherboard of the computer detects these conditions, and a retriggerable monostable multivibrator which activates the LED. The LED is coupled to the triggering logic with by a conductor that need not be added as an additional part or assembly but instead is within an already-existing assembly such as the power supply.

Abstract: The invention provides a duplex processor arrangement wherein the processors are only pseudo-synchronized to each other. Each processor is provided with its own independent clock circuit and the two clock circuits operate at the same nominal frequency. A circuit means is provided for periodically forcing a rendezvous between processors whereat a controller circuit ensures that the processors have processed the same information since the last rendezvous. Each processor comprises a match circuit including memory means connected to store address/data information related to instructions performed by the processors. Each match circuit compares the information from the processors and generates an alarm signal upon a mismatch.