Patents Examined by Calvin M Brien
-
Patent number: 9755782Abstract: An apparatus is provided. The apparatus comprises a polynomial register having a plurality of bits, a first bus, a second bus, and a transceiver that is coupled to the first bus, the second bus, and the polynomial register. The polynomial register is configured to store a user-defined polynomial, and the transceiver includes a pseudorandom bit sequence (PRBS) generator is configured to generate a scrambled signal from the user-defined polynomial and a PRBS checker that is configured to generate a descrambled signal from a second signal using the user-defined polynomial.Type: GrantFiled: July 28, 2015Date of Patent: September 5, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Seuk B. Kim, Tpinn R. Koh
-
Patent number: 9747110Abstract: Circuitry operating under a floating-point mode or a fixed-point mode includes a first circuit accepting a first data input and generating a first data output. The first circuit includes a first arithmetic element accepting the first data input, a plurality of pipeline registers disposed in connection with the first arithmetic element, and a cascade register that outputs the first data output. The circuitry further includes a second circuit accepting a second data input and generating a second data output. The second circuit is cascaded to the first circuit such that the first data output is connected to the second data input via the cascade register. The cascade register is selectively bypassed when the first circuit is operated under the fixed-point mode.Type: GrantFiled: May 20, 2015Date of Patent: August 29, 2017Assignee: Altera CorporationInventor: Martin Langhammer
-
Patent number: 9720650Abstract: A method and an assemblage for post-processing an output of a random source of a random generator are presented. In the method, an output signal of the random source is compressed, thereby yielding a sequence of compressed signal values that are checked in terms of their distribution.Type: GrantFiled: July 7, 2014Date of Patent: August 1, 2017Assignee: Robert Bosch GmbHInventors: Matthew Lewis, Eberhard Boehl
-
Patent number: 9684489Abstract: Methods, apparatuses, and computer program products for squaring an operand include identifying a fixed-point value with a fixed word size and a substring size for substrings of the fixed-point value, wherein the fixed-point value comprises a binary bit string. A square of the fixed-point value can be determined using the fixed point value, the substring size, and least significant bits of the fixed-point value equal to the substring size.Type: GrantFiled: August 31, 2012Date of Patent: June 20, 2017Assignee: Southern Methodist UniversityInventors: Mitchell A. Thornton, Saurabh Gupta
-
Patent number: 9645972Abstract: A butterfly channelizer includes at least two stages. Each stage includes at least one dual-channel module configured to convert an input time domain signal into a second time domain signal of lower bandwidth. At least one clock is configured to generate a clock signal that drives the at least two stages. A first stage has a first number of dual-channel modules and a second stage following the first stage has a second number of dual-channel modules greater than the first number.Type: GrantFiled: July 1, 2014Date of Patent: May 9, 2017Assignee: RAYTHEON COMPANYInventors: Harry B. Marr, Daniel Thompson
-
Patent number: 9632752Abstract: The present system and method relate to a system for performing a multiplication. The system is arranged for receiving a first data value, and comprises means for calculating at run time a set of instructions for performing a multiplication using the first data value, storage means for storing the set of instructions calculated at run time, multiplication means arranged for receiving a second data value and at least one instruction from the stored set of instructions and arranged for performing multiplication of the first and the second data values using the at least one instruction.Type: GrantFiled: December 20, 2012Date of Patent: April 25, 2017Assignees: IMEC, Katholieke Universiteit Leuven, KU LEUVEN R&D, Samsung Electronics Co., Ltd.Inventors: Robert Fasthuber, Praveen Raghavan, Francky Catthoor
-
Patent number: 9619206Abstract: The present invention discloses a pseudo-random bit sequence (PRBS) generator which outputs the entire datapath, or entire pseudo-random bit sequence, over one single clock cycle. This is accomplished by removing redundancy, or any redundant exclusive-or gates from linear feedback shift registers; using logic to identify the critical path and optimal shift for the critical path; and dividing the datapath into several pipeline stages to increase the clock rate (i.e., transmission speed).Type: GrantFiled: April 23, 2014Date of Patent: April 11, 2017Assignee: Altera CorporationInventor: Junjie Yan
-
Patent number: 9612794Abstract: Software implementations are provided for performing IQ imbalance correction and/or RF equalization. An input signal, x, is processed in software by executing a vector convolution instruction to apply the input signal, x, to a first complex FIR filter that performs one or more of RF equalization and IQ imbalance correction; and executing a vector convolution instruction to apply a conjugate x* of the input signal, x, to a second complex FIR filter that performs the one or more of RF equalization and IQ imbalance correction, wherein the second complex FIR filter is in parallel with the first complex FIR filter. The first and second complex FIR filters have complex coefficients and the input signal comprises a complex signal.Type: GrantFiled: October 26, 2012Date of Patent: April 4, 2017Assignee: Intel CorporationInventors: Kameran Azadet, Joseph H. Othmer, Meng-Lin Yu
-
Patent number: 9563403Abstract: A random number generating device of the present disclosure includes: an arithmetic random number generator that generates an arithmetic random number sequence; an arithmetic random number converter that sequentially reads at least one arithmetic random number from the arithmetic random number sequence and converts a value of the read arithmetic random number into a voltage or current value of at least two predetermined levels of gray scale having an identical polarity; a hysteresis unit that outputs values depending on a presently-input voltage or current value and a previously-input voltage or current value with respect to the sequentially-input voltage or current value; and a threshold processor that binarizes the output of the hysteresis unit.Type: GrantFiled: December 12, 2014Date of Patent: February 7, 2017Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Michihito Ueda, Yu Nishitani, Yukihiro Kaneko, Ayumu Tsujimura
-
Patent number: 9547475Abstract: According to one embodiment, a random number generating circuit includes first to N-th oscillating circuits (N is a natural number equal to 2 or greater), first to N-th latch circuits that latch outputs of the first to N-th oscillating circuits by a first clock having a first frequency, first to N-th exclusive OR circuits, (N+1)-th to (2×N)-th latch circuits that latch outputs of the first to N-th exclusive OR circuits by the first clock, an (N+1)-th exclusive OR circuit that outputs an exclusive OR of outputs of the (N+1)-th to (2×N)-th latch circuits, and an M-bit shift register that converts serial data output from the (N+1)-th exclusive OR circuit into M-bit parallel data (M is a natural number equal to 2 or greater) by a second clock having a second frequency.Type: GrantFiled: November 21, 2013Date of Patent: January 17, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Shinichi Yasuda, Tetsufumi Tanamoto, Noriko Inoue, Akira Tomita, Ryusuke Murakami, Atsushi Shimbo
-
Patent number: 9524143Abstract: A data processing apparatus and method of operating such a data processing apparatus are provided, for responding to a division instruction to perform a division operation to generate a result value by dividing an input numerator specified by the division instruction by an input denominator specified by the division instruction. The input numerator and input denominator are binary values. The apparatus comprises division circuitry configured to generate the result value by carrying out the division operation, power-of-two detection circuitry configured to signal a bypass condition if the input denominator has a value given by ±2N, where N is a positive integer, and bypass circuitry configured, in response to signalling of the bypass condition, to cause the division circuitry to be bypassed and to cause the result value to be generated as the input numerator shifted by N bits.Type: GrantFiled: June 26, 2014Date of Patent: December 20, 2016Assignee: ARM LimitedInventors: Neil Burgess, David Raymond Lutz
-
Patent number: 9501260Abstract: A barrel shifter uses a sign magnitude to 2's complement converter to generate decoder signals for its cascaded multiplexer selectors. The sign input receives the shift direction and the magnitude input receives the shift amount. The sign magnitude to 2's complement converter computes an output result as a 2's complement of the shift amount using the shift direction as a sign input, assigns a first portion (most significant bit half) of the output result to a first decoder signal, and assigns a second portion (least significant bit half) of the output result to a second decoder signal. The encoding scheme using a sign magnitude to 2's complement converter allows the decoder circuits to be relatively simple, for example, 3-to-8 decoders for a 64-bit operand value rather than the 4-to-9 decoder required in a conventional barrel shifter, leading to faster operation, less area, and reduced power consumption.Type: GrantFiled: December 3, 2013Date of Patent: November 22, 2016Assignee: International Business Machines CorporationInventor: Takeo Yasuda
-
Patent number: 9477442Abstract: A processor includes: an exponent generating unit that generates an exponent part of a coefficient represented by a floating point number format based on a first part of received input data, the coefficient being obtained when an exponential function is decomposed into a series operation and the coefficient for the series operation; a storage unit that stores a mantissa part of the coefficient; a constant generating unit that reads constant data corresponding to a second part of the input data from the storage unit; and a selecting unit that selects and outputs the constant data from the constant generating unit when an instruction to be executed is a coefficient calculation instruction for calculation of the coefficient of the exponential function.Type: GrantFiled: September 8, 2014Date of Patent: October 25, 2016Assignee: FUJITSU LIMITEDInventor: Mikio Hondo
-
Patent number: 9471542Abstract: The present invention discloses a parameter generating device and the method thereof to generate a parameter for circuit operation in which the parameter corresponds to an N degree polynomial of a characteristic curve while said N is a positive integer. The parameter generating device comprises: a storage circuit to store at least N+1 initial values that are determined by a start value and a unit variation amount; and a parameter calculating circuit, coupled to the storage circuit, to carry out addition calculation for at least [(K?1)×N+1] time(s) if a multiple K is positive or subtraction calculation for at least ?K×N time(s) if the multiple K is negative, so as to generate the aforementioned parameter, wherein the multiple K is derived from a difference divided by the unit variation amount while the difference is a current value minus the start value.Type: GrantFiled: July 3, 2014Date of Patent: October 18, 2016Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Ching-Yao Su, Liang-Wei Huang, Shih-Wei Wang, Wan-Chun Huang
-
Patent number: 9465583Abstract: A method, system, and computer program product for random number generation using a network of mobile devices are provided in the illustrative embodiments. From a set of mobile devices, a corresponding set of data packets is received. A presence of raw sensor data is detected in a first data packet received from a first mobile device in the set of mobile devices. The raw sensor data comprises data corresponding to changing value of an output of a sensor in a set of sensors installed in the first mobile device. The raw sensor data is separated from the first data packet, resulting in an original data packet. A first random number is generated using the raw sensor data.Type: GrantFiled: October 4, 2013Date of Patent: October 11, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Thomas Henry Osiecki, Jan Simon Rellermeyer, Mark William Stephenson
-
Patent number: 9465578Abstract: A system and method are provided for performing 32-bit or dual 16-bit floating-point arithmetic operations using logic circuitry. An operating mode that specifies an operating mode for a multiplication operation is received, where the operating mode is one of a 32-bit floating-point mode and a dual 16-bit floating-point mode. Based on the operating mode, nine recoding terms for a mantissa of at least one floating-point input operand are determined. A dual-mode multiplier array circuit that is configurable to generate partial products for either one 32-bit floating-point result or for two 16-bit floating-point results computes the partial products based on the nine recoding terms. The partial products are processed to generate an output based on the operating mode.Type: GrantFiled: December 13, 2013Date of Patent: October 11, 2016Assignee: NVIDIA CorporationInventors: David C. Tannenbaum, Srinivasan Iyer
-
Patent number: 9459834Abstract: A true random number generator (TRNG) uses sources of uncertainty found within graphics processing units (GPUs) together with signal processing techniques, for example histogram equalization, to obtain maximum entropy.Type: GrantFiled: February 8, 2012Date of Patent: October 4, 2016Inventors: Parimala Thulasiraman, Ruppa K. Thulasiram, Jose Juan Mijares Chan, Bhanu Sharma, Jiaqing Lv, Gabriel Thomas
-
Patent number: 9448768Abstract: A modular multiplier and a modular multiplication method are provided. The modular multiplier includes: a first register which stores a previous accumulation value calculated at a previous cycle; a second register which stores a previous quotient calculated at the previous cycle; a quotient generator which generates a quotient using the stored previous accumulation value output from the first register; and an accumulator which receives an operand, a bit value of a multiplier, the stored previous accumulation value, and the stored previous quotient to calculate an accumulation value in a current cycle, wherein the calculated accumulation value is updated to the first register, and the generated quotient is updated to the second register.Type: GrantFiled: March 11, 2013Date of Patent: September 20, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong Ki Lee, Jonghoon Shin, KyoungMoon Ahn, Ji-Su Kang, Sun-Soo Shin
-
Patent number: 9425826Abstract: A method of generating an interleaved symbol sequence location from a symbol location of a symbol sequence comprises determining the interleaved symbol location based on an interleaver sequence function which relates a linear symbol location to the interleaved symbol location. This is done by acquiring values of the interleaver sequence function in quotient and remainder form and then calculating the interleaved symbol location by performing operations of the interleaver sequence function in quotient and remainder form.Type: GrantFiled: November 2, 2012Date of Patent: August 23, 2016Assignee: BlackBerry LimitedInventor: Damian Kelly Harris-Dowsett
-
Patent number: 9411756Abstract: Function approximation circuitry approximates an arbitrary function F over discrete inputs. Discrete values of the function F are stored in a lookup table (LUT) component for various inputs. An addressing module generates an address from an input. An interpolation factor module generates an interpolation factor from the input. An interpolation module generates an output, which is an approximate value of the function F for the input, from the interpolation factor, and from outputs of the LUT component when the LUT component is addressed by the address.Type: GrantFiled: June 18, 2012Date of Patent: August 9, 2016Assignee: BLACKBERRY LIMITEDInventors: Marco Paulo dos Santos Nogueira, Stephen Arnold Devison