Patents Examined by Carl J. Arbee
  • Patent number: 6763578
    Abstract: A method and apparatus for fabricating known good semiconductor dice are provided. The method includes the steps of: testing the gross functionality of dice contained on a semiconductor wafer; sawing the wafer to singulate a die; and then testing the die by assembly in a carrier having an interconnect adapted to establish electrical communication between the bond pads on the die and external test circuitry. The interconnect for the carrier can be formed using different contact technologies including: thick film contact members on a rigid substrate; self-limiting contact members on a silicon substrate; or microbump contact members with a textured surface. During assembly of the carrier, the die and interconnect are optically aligned and placed into contact with a predetermined contact force. This establishes an electrical connection between the contact members on the interconnect and the bond pads of the die.
    Type: Grant
    Filed: November 20, 1997
    Date of Patent: July 20, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Warren Farnworth, Alan Wood
  • Patent number: 6317973
    Abstract: In a mounting system including a loading station having a transport conveyor for conveying printed circuit boards, a mounting machine for fabricating circuit devices by attaching electronic assemblies on printed circuit boards supplied thereto from said loading station, and a unloading station having a transport conveyor for conveying circuit devices supplied thereto from the mounting machine, the loading station includes a discriminating device for discriminating the kind or type of printed circuit boards and generating a discrimination signal for instructing the kind or type of the printed circuit board. A mounting process in the mounting machine in selectively set by the discrimination signal from the discriminating device. According to this mounting system, even when many kinds of circuit devices are fabricated by many kinds of printed circuit boards, mounting processes can be successively carried out by one mounting line.
    Type: Grant
    Filed: June 14, 1999
    Date of Patent: November 20, 2001
    Assignee: Sony Video (M) SDN.BHD
    Inventors: Tokio Kuriyama, Masao Tomioka
  • Patent number: 6145193
    Abstract: A squib connector socket assembly for automotive air bags includes a shorting clip assembly. The squib connector socket assembly holds a pair of igniter pins of a squib assembly which are connectable to a pair of terminals in a squib connector which plugs into the socket assembly. To prevent accidental firing when the squib connector is removed, the igniter pins are shorted by a shorting clip having a pair of resilient, bowed beams which are independently biassed into contact with the pins. The shorting clip is fixedly retained within a plastic socket insert. The socket insert and squib assembly are assembled within a metal socket which is roll crimped about the insert and squib assembly to form an inseparable, integral squib connector socket assembly.
    Type: Grant
    Filed: November 12, 1998
    Date of Patent: November 14, 2000
    Assignee: Thomas & Betts International, Inc.
    Inventor: Bradford K. Gauker
  • Patent number: 6049971
    Abstract: A method for fabricating a lead frame that includes a platform attached thereto for mounting a chip. A base frame is provided for mounting chips of various sizes. The base frame includes connection leads extending toward a central portion, which is substantially of the size of the smallest chip to mount. Connection leads are cut-out about the central portion to form an opening corresponding to the size of the chip to be mounted. A platform is soldered to at least two support leads to form the lead frame.
    Type: Grant
    Filed: June 13, 1997
    Date of Patent: April 18, 2000
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Luc Petit
  • Patent number: 5946794
    Abstract: A composite microwave circuit module includes a multilayer dielectric substrate, upper- and lower-surface grounds, an antenna pattern, a plurality of shield via holes, and a large number of first holes. The upper- and lower-surface grounds are formed on upper and lower surfaces of the multilayer dielectric substrate, respectively, and the upper-surface ground has an opening portion for waveguide coupling. The antenna pattern is formed on an interlayer of the multilayer dielectric substrate by a high-frequency signal line in correspondence with the opening portion. The plurality of shield via holes are formed around the antenna pattern and filled with a filler material to form a pseudo waveguide structure. The first holes have cavities formed in the multilayer dielectric substrate in correspondence with the pseudo waveguide structure between the antenna pattern and the opening portion of the upper-surface substrate. A method of manufacturing this circuit module is also disclosed.
    Type: Grant
    Filed: June 19, 1997
    Date of Patent: September 7, 1999
    Assignee: NEC Corporation
    Inventors: Takao Koizumi, Yuhei Kosugi
  • Patent number: 5884398
    Abstract: Resilient contact structures are mounted directly to bond pads on semiconductor dies, prior to the dies being singulated (separated) from a semiconductor wafer. This enables the semiconductor dies to be exercised (e.g., tested and/or burned-in) by connecting to the semiconductor dies with a circuit board or the like having a plurality of terminals disposed on a surface thereof. Subsequently, the semiconductor dies may be singulated from the semiconductor wafer, whereupon the same resilient contact structures can be used to effect interconnections between the semiconductor dies and other electronic components (such as wiring substrates, semiconductor packages, etc.). Using the all-metallic composite interconnection elements of the present invention as the resilient contact structures, burn-in can be performed at temperatures of at least 150.degree. C., and can be completed in less than 60 minutes.
    Type: Grant
    Filed: April 15, 1997
    Date of Patent: March 23, 1999
    Assignee: Form Factor, Inc.
    Inventors: Benjamin N. Eldridge, Gary W. Grube, Igor Y. Khandros, Gaetan L. Mathieu
  • Patent number: 5850688
    Abstract: An electronic element which is free of many of the impurities that tend to adversely affect its operation. The electronic element is hermetically sealed in a space formed by a framework having a first and second plate directly joined to its sides. Directly joining the first and second plates to the framework prevents splashes of adhesive and soldering material from effecting the operation of the electronic element.
    Type: Grant
    Filed: March 19, 1997
    Date of Patent: December 22, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Daizo Ando, Tadashi Nakamura, Shinji Umeda, Kunihiko Oishi