Patents Examined by Carl J. Arles
  • Patent number: 4953289
    Abstract: A flat conductor of indeterminate length having a generally rectangular cross-section is terminated by forming a terminal which includes a seamless tubular barrel portion having a cylindrical bore, flattening the barrel portion to alter the cross-sectional configuration of the bore to generally complement the cross-sectional configuration of the conductor to be terminated, inserting the end portion of the conductor into the flattened barrel and swaging opposite sides of the flattened barrel in a controlled manner to simultaneously form indentations in opposite sides of the barrel which project into the bore and deform associated opposite flat sides of the end portion received therein.
    Type: Grant
    Filed: June 5, 1989
    Date of Patent: September 4, 1990
    Assignee: Pyle Overseas B.V.
    Inventors: Daniel J. Schreck, Ronald G. Ehrmann
  • Patent number: 4893403
    Abstract: A method of aligning integrated circuit chips on a substrate, such as a circuit board, for joinder by means of solder bumps. A stencil mask forms a transfer plate with holes in the same locations as solder bumps on the circuit board. The transfer plate is used to lift integrated circuit chips with metal contact regions loosely seated in holes in another mask, forming a die array plate. Vacuum is applied behind the transfer plate to pick up chips which have been seated on the die array plate. The chips are then moved over the circuit board and deposited onto the solder bumps previously formed and then joined thereto. The transfer plate and the die array plate have hole patterns in the same locations as yet another stencil mask, used for solder deposition in forming the solder bumps.
    Type: Grant
    Filed: April 15, 1988
    Date of Patent: January 16, 1990
    Assignee: Hewlett-Packard Company
    Inventors: Bruce Heflinger, Kevin Douglas
  • Patent number: 4890382
    Abstract: The present invention constitutes an apparatus for assembling multiple electrical contacts and filler elements into an electrical connector. The apparatus includes a filler assembly for automatically installing filler elements into the holes within the electrical connector which are to be unoccupied by electrical contacts, and a guide assembly which is functional for assisting the operator in manually inserting the electrical contacts into the correct holes within the connector by providing a visual indication of the holes into which the contacts should be inserted. The filler and guide assemblies operate on connectors held into position on a turntable-like indexing plate which allows the connectors to be rotated alternatively into position with respect to each of the assemblies. The filler assembly includes one or more filler element inserter tools which are adapted for inserting filler material from strands of such material into the holes within the connectors so as to form installed filler elements.
    Type: Grant
    Filed: December 28, 1988
    Date of Patent: January 2, 1990
    Assignee: The Boeing Company
    Inventors: Leslie A. Anderson, Eric J. Selby, David L. Wagner, Alfred E. Walter, Jr.
  • Patent number: 4868980
    Abstract: A printed circuit board for mounting and connecting a plurality of semiconductor devices is disclosed and includes a planar insulating substrate having multiple conductive layers disposed in overlying relationship within the planar substrate. A plurality of parallel rows of apertures for wire-wrap, quick-connect or stitch-wire contacts are provided for mounting integrated circuits. One side of the printed circuit board includes a plurality of power and ground connections disposed between each pair of parallel rows of apertures so that filter capacitors may be mounted under each integrated circuit, thereby conserving printed circuit board space. In a preferred mode of the present invention, alternate ones of the conductive layers are coupled to a source of electrical power while all remaining conductive layers are grounded. At least two adjacent conductive layers are then utilized to minimize parasitic capacitance by completely surrounding each aperture with a portion of conductive material.
    Type: Grant
    Filed: July 12, 1988
    Date of Patent: September 26, 1989
    Assignee: LTV Aerospace & Defense Company
    Inventor: Grady A. Miller, Jr.
  • Patent number: 4866841
    Abstract: An integrated circuit chip carrier with pin grid array is provided with at least two layers of plastics material on the upper of which is provided a central chip location area and a series of metallized areas provided by printed circuit board methods to a series of metallized holes disposed inwardly of the edges of the carrier, a wall of plastics material being disposed round the edges of said upper layer to form a central cavity, the lower layer of plastics material bonded to said upper layer having a series of openings for a pin grid array and an intermediate metallized printed circuit layer disposed between said upper and lower layers to provide electrical conductive paths from the metallized holes to the openings and pins extending downwardly from said lower layer with heads mounted in said openings said array of pins being capable of being across the entire under surface of the carrier. The structure provides superior arrays of pins and similar techniques for construction.
    Type: Grant
    Filed: September 15, 1988
    Date of Patent: September 19, 1989
    Assignee: Advanced Semiconductor Packages Ltd.
    Inventor: John B. Hubbard
  • Patent number: 4851060
    Abstract: Magnet wire substrates (1) are described having a layer of polyester tape (2) wrapped thereon, including a layer of spirally wrapped and bonded polyester insulation tape (3) as the outermost layer. The two tape layers are made up of amorphous (4) and crystalline (5) segments unbonded to the wire and bonded to each other to provide the requisite electrical properties and improved physical properties including increased flexibility and ease of strippability. A single multilayer polyester insulation tape can also be used with similar properties and reduced thickness.
    Type: Grant
    Filed: August 12, 1987
    Date of Patent: July 25, 1989
    Assignee: Essex Group, Inc.
    Inventors: Ivan W. Wade, Jr., John D. Hessler, Harry E. Eloph
  • Patent number: 4776089
    Abstract: An installation tool for mounting a loadbreak reducing tap plug in a high voltage "T"-type connector of the type including a cable connector having a threaded opening, the plug having a threaded end adapted to be mounted in the threaded opening of the cable connector and a threaded bolt extending through the threaded end of the plug, the threaded bolt having a wrenching opening and being rotated by a wrenching tool for connecting the plug to a bushing, the installation tool comprising a shaft having a threaded end corresponding to the threaded opening in the connector and a threaded opening corresponding to the threaded bolt, whereby the threaded end of the installation tool can be mounted in the threaded opening in the connector, the threaded bolt can be mounted in the threaded opening in the installation tool, and the threaded end of the plug can be drawn into alignment with the threaded opening in the connector when the installation tool is backed out of the threaded opening in the connector.
    Type: Grant
    Filed: September 24, 1987
    Date of Patent: October 11, 1988
    Assignee: RTE Corporation
    Inventors: Randall R. Schoenwetter, John M. Makal, Edward L. Sankey
  • Patent number: 4776088
    Abstract: Surface mounted electrical components are typically assembled on printed wiring boards by automatic machines. It is important that the machines accurately move with respect to both X and Y rotational axes in order to insure that components are positioned precisely on connector pads of the printed wiring board being assembled. In accordance with the instant invention, a gauge is used to facilitate convenient accuracy checks. The gauge is a glass substrate on which grids of 0.005 inch lines are scribed to form location and orientation fields where components are to be placed. The grids are referenced from either fiducial marks or the edge of the substrate to establish known positions within the grids. The equipment to be evaluated is programmed to place components in known positions and the components are held in place by tacky adhesive that is sprayed on the substrate prior to placing the components.
    Type: Grant
    Filed: November 12, 1987
    Date of Patent: October 11, 1988
    Assignee: The United States of America as represented by the United States Department of Energy
    Inventors: Peter M. Biggs, Linda K. Dancer, Simon S. Yerganian
  • Patent number: 4761874
    Abstract: A method of making a magnetic recording medium comprises a first step of polishing a surface of a strip-like magnetic recording medium composed of a substrate and a magnetic layer formed on a surface of the substrate by coating a magnetic material onto the surface of the substrate and drying the coated magnetic material, a second step of inspecting the polished surface of the magnetic recording medium for defects, and a third step of punching out the magnetic recording medium, on which the inspection for defects is finished, into a predetermined shape. The first step, the second step and the third step are carried out on the continuous strip-like material.
    Type: Grant
    Filed: April 1, 1987
    Date of Patent: August 9, 1988
    Assignee: Fuji Photo Film Co., Ltd.
    Inventor: Masaaki Utsui
  • Patent number: 4736520
    Abstract: Automatic manufacture of integrated circuit packages including a leadless chip carrier is facilitated by providing, in strip form, flexible tape circuitry having a dielectric layer and a conductive layer. Through selective etching, regularly spaced central openings are formed in the strip for subsequent placement of the leadless chip carriers. The arms are formed in the conductive layer and extend into the openings. Members are formed in the dielectric layer around each opening. A leadless chip carrier is placed in an opening and its pads are bonded to the arms. With the chip carrier thus secured to the strip, its position is controlled by the strip drive means which moves each chip carrier to assembly and testing stations. Electrical testing is accomplished with probes adapted to contact the arms. Temperature cycling and other mechanical tests also are conducted with the chip carrier attached to the tape.
    Type: Grant
    Filed: May 26, 1987
    Date of Patent: April 12, 1988
    Assignee: Control Data Corporation
    Inventor: James B. Morris
  • Patent number: 4631820
    Abstract: An electronic component and a wiring pattern on a printed board are connected electrically by a sheet connector having a conducting layer formed on a surface of an insulating sheet. This provides a mounting assembly for an electronic component which can make simultaneous connection easily and accurately between electrodes of the electronic component, and between electrodes of the printed board, as well as connecting the electronic component and the printed board.
    Type: Grant
    Filed: August 9, 1985
    Date of Patent: December 30, 1986
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yuji Harada, Hayato Shinohara
  • Patent number: 4471527
    Abstract: A method and apparatus for producing a stranded cable. The wire stretching step and annealing steps which have been performed independently prior to the twisting step in the field of stranded cable production are combined in the invented apparatus. The rotary element defines an annular space in cooperation with a shoe member such that the cross sectional area of the annular space decreases progressively. The roughened wire guided into the annular space via the shoe member is press molten and subjected to extrusion moulding to obtain a plurality of wires, which in turn are twisted together. Since the stretching and annealing are performed by a single apparatus, shop space conventionally required for device installation is reduced.
    Type: Grant
    Filed: November 5, 1981
    Date of Patent: September 18, 1984
    Assignee: Yazaki Corporation
    Inventor: Tamotu Nishijima
  • Patent number: 4454651
    Abstract: A method of fabricating a wire harness, the invention comprises several steps. The connectors are positioned at desired locations at a first station. Then wires in lengths dictated by the dimensions of the finished harness are run between predetermined terminal element locations at the connectors. The various wires are fixed in the respective holding means associated with the predetermined terminal element locations so that prior to electrical termination of the wires, the partially completed harness can be moved to a station remote from the first station with the wires maintained relative to the entrances of their corresponding wire-receiving slots.
    Type: Grant
    Filed: October 25, 1979
    Date of Patent: June 19, 1984
    Assignee: Panduit Corp.
    Inventors: Jack E. Caveney, Roy A. Moody
  • Patent number: 4449292
    Abstract: The compact circuit package (11) includes an insulating housing (12) providing a circuit retaining cavity (19) substantially surrounded by a pair of spaced side walls (15, 16) each terminating at a first rim (21, 22) and a second pair of spaced side walls (17, 18) each terminating at a second rim (24, 25). Each of the side walls provides an abutment (28, 31, 34) which limits the depth of entry of an electrically insulating, heat conducting substrate (30) into the cavity (19). Outer portions (44, 45) of a first pair of side wall rims (21, 22) are removed such as by a sander (46) to form a clamping surface (48) which includes an outer surface (42) of substrate (30) and reduced end portions (49, 50) of the pair of the side wall rims (21, 22) to permit increased substantial clamping pressures to a substantially planar external heat dissipating object (51) without damaging the substrate (30) and the side walls (15, 16, 17, 18).
    Type: Grant
    Filed: March 26, 1982
    Date of Patent: May 22, 1984
    Inventor: Lance R. Kaufman
  • Patent number: 4417391
    Abstract: A recording head for use in an electrostatic printer comprises four staggered rows of styli formed by a novel method wherein the styli in the second row are formed between the styli in the first row and the styli in the third and fourth rows are formed by making use of the grooves formed between the styli in the first and second rows. By forming the rows of styli on a cylindrical drum, two recording heads are obtained from each fabrication run wherein the recording head in one set of styli is the mirror image of the recording head in the other set of styli. Should an error occur in the manufacture of the styli by placing the third row of styli in the grooves where the fourth row of styli normally belongs, the resulting recording heads are identical to those obtained with the proper placement of the third and fourth rows with the exception that the position on the drum of each type of recording head is reversed.
    Type: Grant
    Filed: June 8, 1982
    Date of Patent: November 29, 1983
    Assignee: Benson, Inc.
    Inventors: Sherman L. Rutherford, Arthur E. Bliss, Noel J. Schmidt
  • Patent number: 4365411
    Abstract: An apparatus and technique are provided to automatically align an insert for insertion into a hole of a predrilled board. The hole is located by a retractable centering pin on the apparatus to ensure an accurate alignment with the insert, and, once aligned, the insert is inserted into the hole with a force axially applied by the apparatus.
    Type: Grant
    Filed: August 28, 1980
    Date of Patent: December 28, 1982
    Assignee: Bivar, Inc.
    Inventor: Edward M. Muldoon, Jr.