Abstract: A method for forming a semiconductor device. A substrate is provided, wherein the substrate has recessed gates and deep trench capacitor devices therein. Protrusions of the recessed gates and upper portions of the deep trench capacitor devices are revealed. Spacers are formed on sidewalls of the upper portions and the protrusions. Buried portions of conductive material are formed in spaces between the spacers. The substrate, the spacers and the buried portions to form parallel shallow trenches are patterned to form parallel shallow trenches for defining active regions. A layer of dielectric material is formed in the shallow trenches, wherein some of the buried portions serve as buried contacts.

Abstract: Optoelectronic device packaging assemblies and methods of making the same are described. In one aspect, an optoelectronic device packaging assembly includes an electrical sub-mount that includes a mounting area, a device turning mount, and a light-emitting device. The device turning mount has a sub-mount mounting side that is attached to the mounting area of the electrical sub-mount and a device mounting side that has a device mounting area that is oriented in a plane that is substantially perpendicular to the mounting area of the electrical sub-mount. The light-emitting device includes one or more semiconductor layers that terminate at a common light-emitting surface and are operable to emit light from the light-emitting surface. The light-emitting device is attached to the device mounting area of the device turning mount with the light-emitting surface oriented in a plane that is substantially parallel to the mounting area of the electrical sub-mount.

Abstract: A method for forming a shallow trench isolation layer that includes: forming a pad oxide on a substrate; forming a hard mask silicon nitride on the pad oxide; forming a moat pattern on the pad oxide and hard mask; etching partially the pad oxide and hard mask with the moat pattern to open the silicon nitride; and ashing process for removing the moat pattern.

Abstract: A method of manufacturing a transistor includes the step of forming on a substrate a source electrode and drain electrode by selective electroless plating after patterning a charge control agent attached to the substrate using light, and the step of forming an organic semiconductor, a gate insulation layer, and a gate electrode.

Abstract: A substantially planar surface coexposes conductive or semiconductor features and a dielectric etch stop material. In a preferred embodiment, the conductive or semiconductor features are pillars forming vertically oriented diodes. A second dielectric material, different from the dielectric etch stop material, is deposited on the substantially planar surface. A selective etch etches a hole or trench in the second dielectric material, so that the etch stops on the conductive or semiconductor feature and the dielectric etch stop material. In a preferred embodiment the substantially planar surface is formed by filling gaps between the conductive or semiconductor features with a first dielectric such as oxide, recessing the oxide, filling with a second dielectric such as nitride, then planarizing to coexpose the nitride and the conductive or semiconductor features.

Abstract: The invention includes methods for utilizing partial silicon-on-insulator (SOI) technology in combination with fin field effect transistor (finFET) technology to form transistors particularly suitable for utilization in dynamic random access memory (DRAM) arrays. The invention also includes DRAM arrays having low rates of refresh. Additionally, the invention includes semiconductor constructions containing transistors with horizontally-opposing source/drain regions and channel regions between the source/drain regions. The transistors can include gates that encircle at least three-fourths of at least portions of the channel regions, and in some aspects can include gates that encircle substantially an entirety of at least portions of the channel regions.

Abstract: A method of fabricating a semiconductor-on-insulator semiconductor substrate is disclosed that includes providing first and second semiconductor substrates. Either oxygen or nitrogen is introduced into a region adjacent the surface of the first semiconductor substrate and a rare earth and hydrogen are implanted at different energy levels into the second semiconductor substrate to produce a rare earth rich region adjacent the surface and a hydrogen layer spaced from the surface. The surface of the first semiconductor substrate is bonded to the surface of the second semiconductor substrate in a process that includes annealing to react either the oxygen or the nitrogen with the rare earth to form an interfacial insulating layer of either rare earth oxide or rare earth nitride. During the anneal the hydrogen layer is blistered and a portion of the second semiconductor substrate is removed and the surface polished to form a thin crystalline active layer on the interfacial insulating layer.

Abstract: A multilayer interconnection structure includes a first interlayer insulation film, a second interlayer insulation film formed over the first interlayer insulation film, an interconnection trench formed in the first interlayer insulation film and having a sidewall surface and a bottom surface covered with a first barrier metal film, a via-hole formed in the second interlayer insulation film and having a sidewall surface and a bottom surface covered with a second barrier metal film, an interconnection pattern filling the interconnection trench, and a via-plug filling the via-hole, wherein the via-plug makes a contact with a surface of the interconnection pattern, the interconnection pattern has projections and depressions on the surface, the interconnection pattern containing therein oxygen atoms along a crystal grain boundary extending from the surface toward an interior of the interconnection pattern with a concentration higher than a concentration at the surface.

Abstract: Photoelectric converters are arranged two-dimensionally in a semiconductor substrate. A planarizing layer, a light shielding film, a further planarizing layer and condenser lenses are formed sequentially on the semiconductor substrate and the photoelectric converters. The light shielding film has apertures at positions corresponding to the photoelectric conversion devices. Multilayer interference filters that transmit either a red, green or blue wavelength component of light are disposed in the apertures.

Abstract: The top surfaces of conductive features are treated with a treatment solution before forming a passivation layer over the conductive features. The treatment solution includes a cleaning solution and a chemical grafting precursor. The treatment solution may also include a leveling and wetting agent to improve coverage uniformity of the chemical grafting precursor. The method results in a uniform passivation layer formed over conductive features across a surface of a workpiece.

Abstract: A semiconductor device includes a substrate, an inter-metal dielectric (IMD) layer over the substrate, and either a nitrogen-containing tetraethoxysilane (TEOS) oxide layer or an oxygen-rich TEOS oxide layer over the IMD layer. The molecular ratio of oxygen in the oxygen-rich TEOS oxide layer is greater than 70%. The IMD layer comprises an extra-low dielectric constant (ELK) layer.

Abstract: A silicon film is formed on a first region and a second region, respectively of a semiconductor substrate; P-type impurities are selectively ion-implanted into the silicon film in the first region; a first annealing is carried out, thereby the P-type impurities implanted in the silicon film are activated; N-type impurities are selectively ion-implanted into the silicon film in the second region, after the first annealing; a silicide film is formed on the silicon film according to a CVD method, after the ion-implantation of the N-type impurities; a second annealing is carried out, thereby gas contained in the silicide film is discharged and the N-type impurities are activated; a barrier metal film and a metal film are formed in this order on the silicide film; and the metal film, the barrier metal film, the silicide film and the silicon film are patterned, thereby a P-type polymetal gate electrode formed in the first region and an N-type polymetal gate electrode formed in the second region.

Abstract: An electronic fabrication process and structure is provided for attaching discrete passive surface mount devices (SMD) to a substrate in a single step. A liquid noflow resin encapsulant containing flux material is dispensed between presoldered pads on a substrate. The SMD, having a pair of electrical contacts, is pressed into said encapsulant so that the electrical contacts make contact with said presoldered pads. Heat is applied to first activate said flux material and then reflow the solder on said presoldered pads to bond said SMD contacts to said presoldered pads. The reflow temperature is maintained for about 180 seconds during which time the resin solidifies. The resin encapsulant fills the space between substrate and SMD and forms fillets around the solder bonded contacts.

Abstract: A method and structure for producing lasers having good optical wavefront characteristics, such as are needed for optical storage includes providing a laser wherein an output beam emerging from the laser front facet is essentially unobstructed by the edges of the semiconductor chip in order to prevent detrimental beam distortions. The semiconductor laser structure is epitaxially grown on a substrate with at least a lower cladding layer, an active layer, an upper cladding layer, and a contact layer. Dry etching through a lithographically defined mask produces a laser mesa of length lc and width bm. Another sequence of lithography and etching is used to form a ridge structure with width w on top of the mesa. The etching step also forming mirrors, or facets, on the ends of the laser waveguide structures. The length ls and width bs of the chip can be selected as convenient values equal to or longer than the waveguide length lc and mesa width bm, respectively.

Abstract: In a first embodiment, Tetraethyl Orthosilicate Si(OC2H5)4 is used at the process temperature of 650° C.±5° C. as film forming material, to decrease crystal defects occurring during deposition. In a second embodiment, annealing is carried out in sparse oxygen gas atmosphere after deposition, to mend crystal defects that occurred during deposition. In a third embodiment, initial temperature of the CVD device is kept at about 400° C., whereby the start of natural oxidation of the deposition surface is prevented and production circumstances of the semiconductor element is not deteriorated. Then, the CVD device is heated up to CVD temperature of about 750° C. or about 650° C., to deposit oxide.

Abstract: This invention is directed to preventing deformation, breakage, and the like of leads in a semiconductor device, reducing the fraction of defects, and making the semiconductor device smaller and thinner. In order to accomplish these objects, in a carrier including a base having a device hole and a plurality of leads for bonding a chip, the leads are provided with thin heat-resistant films.

Abstract: Disclosed is a method of manufacturing a semiconductor device comprising forming an element isolation trench in a semiconductor substrate, coating a polysilazane perhydride solution on the semiconductor substrate having the element isolation trench formed thereon to form a polysilazane perhydride film, the polysilazane perhydride solution comprising dibutyl ether having a butanol concentration of 30 ppm or less, and polysilazane perhydride dissolved in the dibutyl ether, subjecting the polysilazane perhydride film to oxidation in an atmosphere containing water vapor to form a silicon dioxide film, and selectively removing the silicon dioxide film to leave the silicon dioxide film in the element isolation trench to form an element isolating insulation film.

Abstract: Methods are provided for electrochemically depositing copper on a work piece. One method includes the step of depositing overlying the work piece a barrier layer having a surface and subjecting the barrier layer surface to a surface treatment adapted to facilitate deposition of copper on the barrier layer. Copper then is electrochemically deposited overlying the barrier layer.

Abstract: A method and apparatus for encapsulating microelectronic devices. In one embodiment, the method includes removing a portion of encapsulating material that at least partially surrounds a microelectronic substrate by directing a source of laser radiation toward the encapsulating material. The method can further include exposing a surface of the microelectronic substrate, for example, to enhance a rate at which heat is transferred away from the microelectronic substrate. Alternatively, the encapsulating material can be removed to form heat transfer structures, such as pins or ribs, also to enhance a rate at which heat is transferred away from the microelectronic substrate. In still another embodiment, a portion of the encapsulating material or a support member to which the substrate is attached can be removed to define interlocking features that allow one microelectronic substrate package to be stacked on another and to resist relative movement between the two packages.

Abstract: It is an object of the present invention to provide a method for forming an interlayer insulation film suppressing the occurrence of voids in the interlayer insulation film. A method for forming an interlayer insulation film of the present invention, comprising the steps of: (1) forming an etching stopper film of a silicon nitride film on an entire surface including a step part on a semiconductor substrate having the step part with an aspect ratio of ?3; (2) forming an interlayer insulation film of an impurity-doped silicate film on the silicon nitride film; and (3) performing reflow of the interlayer insulation film by a heat treatment, wherein the formation of the silicon nitride film is controlled such that the N—H bond density of the silicon nitride film is 1.0×1022 pieces/cm3 or less.