Abstract: A switching power supply comprises a power converter having a transformer, a low side switch configured to draw current from a supply voltage through a primary winding of the transformer and a high side switch configured to couple the primary winding of the transformer to a snubber capacitor. A controller is configured to synchronously control the opening and closing of the low side switch and the high side switch so as to form a regulated output voltage. A first voltage is generated at a node between the low side switch and the high side switch. The controller is further configured to open the high side switch during each switching cycle when the first voltage reaches a determined level. The determined level is higher than the supply voltage by an amount that is adjusted dependent on a monitored level of the supply voltage.

Abstract: Systems for power conversion, and controllers and methods for operating a power converter. The method includes receiving high-side and low-side primary signals that drive primary transistors of a power converter. The method also includes receiving a combined drain voltage signal for high-side and low-side synchronous rectifier (SR) transistors of the power converter. The method further includes generating a high-side SR signal based on the low-side primary signal and generating a low-side SR signal based on the high-side primary signal. The method also includes determining high-side and low-side body diode conduction times based on the combined drain voltage signal. The method further includes adjusting the high-side SR signal based on the high-side body diode conduction time and adjusting the low-side SR signal based on the low-side body diode conduction time.

Abstract: A fault-responsive power system and method using asynchronous load current switching. A first supply-side current that flows from a power supply into a first conductor, which electrically couples the power supply to a load, is measured. Power is delivered to the load by modulating a first remote-side current on and off, with the remote-side current entering the load from the first conductor. Once it is determined that the first supply-side current has met or exceeded a magnitude threshold for at least a duration threshold, the first supply-side current is reduced such that the first supply-side current is less than the magnitude threshold. A data signal may also be transmitted by embedding a data signal in the first remote-side current through the modulation of the first remote-side current, and demodulating the data signal in the first supply-side current.

Abstract: A method for regulating voltage in an electronic device includes receiving, at a power stage, a gate voltage from an input terminal, and delivering an output voltage and an output current to a processing module based on the gate voltage. The gate voltage is compensated by comparing the output voltage with a reference voltage to produce a compensated gate voltage. The gate voltage compensation is sped by up stabilizing the output voltage during transitions between operational modes using a first compensation stage, decoupling a second compensation stage from the input terminal when a control signal is asserted to thereby precharge a compensation capacitor to an initial compensation voltage, and coupling the second compensation stage to the input terminal via a compensation resistor when the control signal is deasserted to thereby deliver the initial compensation voltage to the input terminal.

Abstract: A circuit arrangement for a current converter has a half bridge with two series-connected power semiconductor switches in each case. The half bridge has a module with a power semiconductor switch in each case, a first DC voltage terminal, a second DC voltage terminal and an AC voltage terminal. A capacitor is connected in parallel with the half bridge and has a first and second capacitor terminals. A first busbar connects the first DC voltage terminal to the first capacitor terminal, and a second busbar connects the second DC voltage terminal to the second capacitor terminal. The first and the second busbars are arranged as to be spatially parallel and electrically insulated from each other. The circuit arrangement has a resistor connected in series with the capacitor, wherein the resistor is arranged in the first and/or second busbar.

Abstract: A frequency converter has a first intermediate circuit arm on which a positive intermediate circuit potential is present during operation, a second intermediate circuit arm on which a negative intermediate circuit potential is present during operation, and an inverter having first and second input terminals. The inverter has a number of bridge arms, each of which has an upper and a lower semiconductor switching device. The upper and lower switching devices are looped in series between the first and second input terminals. A connection node of the upper and lower switching devices forms an inverter output terminal. A reactor is looped-in between the first circuit arm and the first input terminal. A shunt resistor is looped-in between the second circuit arm and the second input terminal. An evaluation unit detects, based on a voltage across the shunt resistor, a ground fault on the upper semiconductor switching devices of the inverter.

Abstract: A control circuit for controlling a multi-level buck converter having N pairs of switches serially connected between an input terminal and a logic ground, wherein N is an integer equal to or greater than 2. The control circuit has a comparing circuit, a selecting circuit and a delay circuit. The comparing circuit compares a voltage feedback signal indicative of an output voltage signal of the multi-level buck converter with a reference signal to generate a comparing signal. The selecting circuit generates N set signals based on the comparing signal. The delay circuit delays the N set signals to provide N delay set signals to control the N pairs of switches when the output voltage signal falls in ( 1 ± k ? % ) ? 1 N of an input voltage signal of the multi-level buck converter, ( 1 ± k ? % ) ? 2 N of the input voltage signal, . . . , or ( 1 ± k ? % ) ? N - 1 N of the input voltage signal, wherein k is a proportional coefficient.

Abstract: A voltage regulator provides a regulated voltage to a double data rate (DDR) Physical Interface (PHY) including a plurality of delay elements. The voltage regulator includes: an amplifier, for receiving a voltage at a first input terminal and generating an output voltage; a first MOSFET coupled to a supply voltage and a second input terminal of the amplifier; a second MOSFET coupled in parallel with the first MOSFET for generating a first current in response to a first enable signal; a load, coupled to the first MOSFET and the second MOSFET, for generating the regulated voltage; and a load capacitor, coupled in parallel with the load. The first enable signal is generated by inputting a gate enable signal for a delay element of the plurality of delay elements into a delay circuit corresponding to the delay element.

Abstract: A system and method for compensating a faulty switch in a multi-level flying capacitor converter includes a converter capacitor arranged in parallel to an input, a first and second converter switches arranged respectively between first and second ends of the converter capacitor, first and second bypass switches respectively arranged in parallel to the first and second converter switches, wherein operation includes detecting a faulty converter level that includes at least one of the first and second converter switches, discharging all capacitors arranged in parallel to the input of the multi-level converter, wherein all capacitors comprise the converter capacitors and an input capacitor; closing the first and second bypass switches of the faulty converter level; adapting a modulation of the converter switches of the other converter levels; and restarting the multi-level converter.

Abstract: A driver stage configured to switch an output node between a high-side potential and a low-side potential. The driver stage includes a high-side switch arranged between the high-side potential and the output node, a low-side switch arranged between the output node and the low-side potential, and an intermediate circuit arranged between the output node and an intermediate potential, wherein the intermediate potential lies between the high-side potential and the low-side potential. Furthermore, the driver stage includes a control unit configured to operate the driver stage at least in a high-side phase, in a low-side phase and in an intermediate phase.

Abstract: A power converter configured to be connected to three or more voltage parts, includes three or more power-conversion circuitries to be connected to respective ones of the three or more voltage parts, and a multi-port transformer connected to the three or more power-conversion circuitries at respectively different ports. The three or more voltage parts include a vehicle drive battery and a plurality of alternating-current (AC) voltage parts. Each of the plurality of AC voltage parts is configured to provide at least one of power input to a multi-port transformer side and power output from the multi-port transformer side.

Abstract: A method for producing a voltage for an electric motor of a drive of an electrical switch includes producing a DC link direct voltage from a supply voltage and producing the motor voltage by pulse-width modulation of the direct voltage. A tolerance range for changing the direct voltage is specified, and an actual value of the direct voltage is continually measured. After first measuring the actual value, it is stored in a voltage variable. After each additional measurement, it is checked whether the deviation of the actual from the stored value lies within the tolerance range. The actual value is stored if the deviation from the stored value lies outside of the tolerance range. After each storage, a duty cycle of the pulse-width modulation dependent on the actual value is calculated, and the pulse-width modulation occurs with the duty cycle. A power converter is also provided.

Abstract: A method for operating a power electronic converter comprising at least one power semiconductor device is provided. The method comprises the determination of the at least one current limit, by carrying out a first operation if the temperature of the at least one semiconductor device is above an upper temperature threshold in order to decrease the current limit, and by carrying out a second operation if the temperature of the at least one semiconductor device is below a lower temperature threshold in order to increase the current limit.

Abstract: Provided is a power semiconductor element gate driving circuit that performs ON/OFF control on main current of a power semiconductor element having a gate electrode by charging the gate electrode of the power semiconductor element with electric charges and discharging the electric charges on the basis of an inputted gate signal. When the gate signal is switched to an OFF signal, control is performed such that gate current for discharging the electric charges from the gate electrode increases in association with increase in a temperature of the power semiconductor element and decreases in association with increase in the main current.

Abstract: A power switch current sensing circuit includes matching first and second transistors having sources connected to first and second terminals, respectively, of the power switch. A current mirror has a first node coupled to a drain of the first transistor and a second node coupled to a drain of the second transistor. The current mirror sinks a current from the first node equal to a current flowing through the second transistor. A biasing circuit provides a same biasing voltage to the control terminals of the first and second transistors. An output resistance is coupled between the first node and a reference voltage node. A difference between a current flowing through the first transistor and the current sunk by the current mirror circuit from the first node flows through the output resistance. An output voltage produced at the first node is indicative of the current flowing through the power switch.

Abstract: A constant time buck-boost switching converter includes: a power switch circuit for switching a first terminal of an inductor between an input voltage and a ground, and for switching a second terminal of the inductor between an output voltage and the ground; and a modulation control circuit for generating a buck ramp signal and a boost ramp signal and for controlling the inductor according to comparisons of these two ramp signals with an error amplification signal, so as to convert the input voltage to the output voltage. The average levels of the buck ramp signal and the boost ramp signal are both equal to a product of the output voltage multiplied by a predetermined ratio. The upper limit of the buck ramp signal and the lower limit of the boost ramp signal are both equal to a product of the input voltage multiplied by the predetermined ratio.

Abstract: A voltage converter (110, 210) having a first bidirectional voltage line (112, 212), a second bidirectional voltage line (114, 214), a power storage element (L1) arranged between the first bidirectional voltage line and the second bidirectional voltage line, a switch element electronically coupled to the power storage element, a controller (141) for controlling the switch, and the controller configured and arranged to adjust a current flow between the first voltage line and the second voltage line such that a voltage level on the second bidirectional voltage line is substantially maintained at a target DC voltage.

Abstract: In at least one example, an apparatus includes a current sense circuit, an imbalance detector, and a current balancer. The current sense circuit including a first phase input, a second phase input, a first sense output, and a second sense output. The imbalance detector having a detector output, a first detector input, and second detector input. The first detector input is coupled to the first sense output and the second detector input is coupled to the second sense output. The current balancer having a balancer input and a balancer output. The balancer input is coupled to the detector output.

Abstract: Apparatus and method for establishing a stable operating point of a H-bridge with a center shunt switch. The stable operating point lets a circuit connected to the H-bridge outputs work in a more ideal condition. As such, an H-bridge with a stable operating point will yield a higher performance and/or save power. Since common mode is one of the biggest sources of electromagnetic interference, a stable operating point in an H-bridge also suppresses EMI.

Abstract: An LLC resonant converter comprises, an LLC resonant converter circuit with an output line and an input line. The LLC resonant converter circuit includes a switch array operatively connecting between the input line and the output line. A controller is connected to the input line by a feed forward line and connected to a respective gate of each switch in the switch array. The controller includes machine readable instructions configured to cause the controller to receive feed forward input from the input line and control switching of the switch array with a pulse frequency modulation (PFM) switching pattern to regulate voltage of the output line.