Patents Examined by Carlos S Tsai
  • Patent number: 9299036
    Abstract: An example embodiment includes a life pattern detection system. The life pattern detection system includes a sensor, a data acquisition device, and a first processor. The sensor is configured to monitor actions of a user. The data acquisition device is configured to harvest signals from the sensor and produce sensor data. The first processor is configured to receive the sensor data and background data, and to execute a life pattern application including a first series of analytical steps that determines a predictable set of actions from the sensor data and the background data.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: March 29, 2016
    Assignee: STRIIV, INC.
    Inventors: Mark A. Ross, Zongde Qiu, David Jonq Wang, Conway Thomas Chen, Ronald Jen-Chuan Chwang
  • Patent number: 9158297
    Abstract: In a method for generating a measurement program of a product, a CAD file of the product is read and attribute data of the product is obtained from the CAD file. By creating a mesh over the attribute data of the product using a plurality of triangles, the method obtains coordinate information of measuring points of the product from the CAD file, arranges the measuring points of the product into one or more geometrical elements using a curve fitting method, and obtains measuring information of each geometrical element. By integrating the measuring information of each of the one or more geometrical elements into a predefined program model, a measurement program can be generated and displayed on a display device.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: October 13, 2015
    Assignees: HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Chih-Kuang Chang, Xin-Yuan Wu, Jin-Gang Rao
  • Patent number: 7640124
    Abstract: In a delay failure test circuit, a delay failure test between two clock domains among a plurality of clock domains having different operation clock rates is performed. The delay failure test circuit inputs, to a first clock domain, a clock signal having only a launch edge for transferring data from the first clock domain to a second clock domain, and to input, to the second clock domain, a clock signal having only a capture edge for capturing the data.
    Type: Grant
    Filed: March 14, 2007
    Date of Patent: December 29, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Hideaki Konishi, Ryuji Shimizu, Masayasu Hojo, Haruhiko Abe, Satoshi Masuda, Naofumi Kobayashi