Abstract: A microprocessor has an interface between a reorder buffer and a floating point unit, including a retire signal provided by the reorder buffer and a valid signal provided by the floating point unit. When the reorder buffer detects a floating point instruction which is ready to be retired, the reorder buffer pulses the retire signal. When the floating point unit executes the floating point instruction and produces a corresponding instruction result, the floating point unit pulses the valid signal. Upon assertion of both the retire signal and the valid signal, the floating point instruction is retired by the floating point unit. The reorder buffer retires the floating point instruction upon asserting the retire signal. Either the valid signal or the retire signal may be asserted first (in a temporal sense) for the floating point instruction. The receiving unit for the signal asserted first stores the signal in a shift register until the receiving unit detects the particular floating point instruction.