Patents Examined by Chakila D Tillie
  • Patent number: 7374957
    Abstract: A system and method are provided for qualifying or calibrating lithographic apparatus or parts therefor, using a predetermined objective criterion such as Chauvenet's criterion is used to reject measurement points, individually, by field or by substrate.
    Type: Grant
    Filed: July 11, 2005
    Date of Patent: May 20, 2008
    Assignee: ASML Netherlands B.V.
    Inventor: Rene Oesterholt
  • Patent number: 7358131
    Abstract: The invention includes SRAM constructions comprising at least one transistor device having an active region extending into a crystalline layer comprising Si/Ge. A majority of the active region within the crystalline layer is within a single crystal of the crystalline layer, and in particular aspects an entirety of the active region within the crystalline layer is within a single crystal of the crystalline layer. The SRAM constructions can be formed in semiconductor on insulator assemblies, and such assemblies can be supported by a diverse range of substrates, including, for example, glass, semiconductor substrates, metal, insulative materials, and plastics. The invention also includes electronic systems comprising SRAM constructions.
    Type: Grant
    Filed: February 8, 2006
    Date of Patent: April 15, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Arup Bhattacharyya
  • Patent number: 7354853
    Abstract: The invention describes a method for the selective dry etching of tantalum and tantalum nitride films. Tantalum nitride layers (30) are often used in semiconductor manufacturing. The semiconductor substrate is exposed to a reducing plasma chemistry which passivates any exposed copper (40). The tantalum or tantalum nitride films are selectively removed using an oxidizing plasma chemistry.
    Type: Grant
    Filed: July 12, 2005
    Date of Patent: April 8, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Mona M. Eissa, Troy A. Yocum
  • Patent number: 7323357
    Abstract: The invention relates to a method for manufacturing at least one phase change memory cell. The method at least fabricating at least one first lamellar spacer of conductive material, which is electrically coupled to the PCM material of the memory cell; fabricating at least one second lamellar spacer on top of the first lamellar spacer, wherein the second lamellar spacer crosses the first lamellar spacer in the area of the PCM material; partially removing the first lamellar spacer, wherein the second lamellar spacer serves as a hardmask for partially removing the first lamellar spacer, so that the first lamellar spacer forms at least one electrode contacting an area of PCM material.
    Type: Grant
    Filed: November 17, 2005
    Date of Patent: January 29, 2008
    Assignee: Qimonda AG
    Inventor: Harald Seidl