Abstract: Interconnect structures that include a conformal liner repair layer bridging breaches in a liner formed on roughened dielectric material in an insulating layer and methods of forming such interconnect structures. The conformal liner repair layer is formed of a conductive material, such as a cobalt-containing material. The conformal liner repair layer may be particularly useful for repairing discontinuities in a conductive liner disposed on roughened dielectric material bordering the trenches and vias of damascene interconnect structures.

Abstract: An interconnect structure with improved performance and capacitance by providing air gaps inside the dielectric layer by use of a multi-phase photoresist material. The interconnect features are embedded in a dielectric layer having a columnar air gap structure in a portion of the dielectric layer surrounding the interconnect features. The interconnect features may also be embedded in a dielectric layer having two or more phases with a different dielectric constant created. The interconnect structure is compatible with current back end of line processing.

Abstract: A method includes providing a single crystal wafer having MMIC chips. Each chip has an active device in a first surface portion of a semiconductor substrate provided by the wafer and an electrical interconnect having a first portion disposed on a second surface of the semiconductor substrate. The semiconductor substrate structure has a via therethrough, a second portion of the electrical interconnect passing though the via and being electrically connected to the active device. A multilayer interconnect structure is formed on the wafer providing a signal routing section on the second surface portion of a corresponding one of the chips. Each section has dielectric layers and an electrical conductor, such electrical conductor being electrically coupled to the active device to route an electrical signal to such active device. Each chip and the corresponding signal routing section are separated from the wafer.

Abstract: A method for fabricating a thin-film transistor contains successively forming four thin films on a substrate and performing an etching process to pattern the four thin films, wherein the four thin films are a first conductive layer, a first insulation layer, a semiconductor film, and a metal-containing sacrificial layer from bottom to top. A second insulation layer is formed on the substrate and the metal-containing sacrificial layer. Then, a lift-off process is performed to the metal-containing sacrificial layer for simultaneously removing the metal-containing sacrificial layer and the second insulation layer positioned on the metal-containing sacrificial layer. Finally, a second conductive layer is formed on the semiconductor layer for forming a source electrode and a drain electrode.

Abstract: In a method for forming a gate in a semiconductor device, a first preliminary gate structure is formed on a substrate. The first preliminary gate structure includes a gate oxide layer, a polysilicon layer pattern and a tungsten layer pattern sequentially stacked on the substrate. A primary oxidation process is performed using oxygen radicals at a first temperature for adjusting a thickness of the gate oxide layer to form a second preliminary gate structure having tungsten oxide. The tungsten oxide is reduced to a tungsten material using a gas containing hydrogen to form a gate structure. The tungsten oxide may not be formed on the gate structure so that generation of the whiskers may be suppressed. Thus, a short between adjacent wirings may not be generated.

Abstract: Alignment methods of IC device substrates. A first IC device substrate has a first front side for defining a plurality of first IC features, a first backside opposite the first front side, and a first alignment pattern formed on the first front side or the first backside. A second IC device substrate has a second front side for defining a plurality of second IC features, a second backside opposite the second front side, and a second alignment pattern formed on the second front side or the second backside. A first optical detector and a second optical detector are applied to detect the first and second alignment patterns, so as to align the first and second IC device substrates. Specifically, the first and second alignment patterns face toward the first and second optical detectors in opposite directions.