Abstract: A thin-film transistor is provided which prevents the degradation of transistor characteristics due to ion channeling. A thin-film transistor (10) includes thin crystalline silicon (2) including source and drain regions (2a) and a channel region (2b), which are formed on a substrate (1); a gate insulator (3) formed on the crystalline silicon (2); and a gate electrode (4) formed on the gate insulator (3). The gate electrode (4) includes an amorphous layer (5) and a crystalline layer (6).

Abstract: According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises a sacrificial post which, in one exemplary embodiment, is situated between first and second link spacers. The bipolar transistor also comprises a conformal layer situated over the sacrificial post. The conformal layer may comprise silicon oxide, for example. According to this exemplary embodiment, the bipolar transistor further comprises a sacrificial planarizing layer situated over the conformal layer, the sacrificial post, and the base. The sacrificial planarizing layer has a first thickness in a first region between the first and second link spacers and a second thickness in a second region outside of the first and second link spacers, where the second thickness is generally greater than the first thickness. Another embodiment is a method that achieves the above-described bipolar transistor.

Abstract: A non-volatile memory device and a fabrication method thereof are provided. A first polysilicon layer, an inter-gate dielectric layer, a second polysilicon layer and a capping layer are stacked sequentially. A first opening is formed through the inter-gate dielectric layer, the second polysilicon layer and the capping layer, thereby exposing the first polysilicon layer. A second opening is formed through the capping layer, thereby exposing the second polysilicon layer. On the resultant structure, a metal layer is formed and then thermally treated. As a result a metal silicide layer can be formed on the exposed portion of the first polysilicon layer and the exposed portion of the second polysilicon layer.

Abstract: A method of reducing the planarization defects produced during the manufacture of semiconductor devices. A sacrificial layer, having defects produced during a interconnection feature planarization step, is removed prior to the formation of subsequent layers to reduce the replication of unwanted defects.

Abstract: A low temperature in-situ precleaning process for a semiconductor surface is disclosed. Ambient reactant gases, such as NF.sub.3 and GeH.sub.4, having a partial pressure of between approximately 10.sup.-8 and 700 Torr, are pulsed in a batch furnace at temperatures in the approximate range of 250 to 950 degrees Celsius and pressure in the approximate range of 4.times.10.sup.3 to 20.times.10.sup.3 Torr. This forms material on the surface that easily vaporizes in that temperature and pressure range, providing a clean surface for formation of the next layer. A similar in-situ cleaning process is performed at temperature ranges of between approximately 300 to 1,000 degrees Celsius for the equipment utilized in processing semiconductor substrates.