Patents Examined by Chandra Chaudhani
  • Patent number: 5891780
    Abstract: A semiconductor device comprises a semiconductor substrate formed with at least one well containing impurity ions of either a first conductivity type or a second conductivity type; a plurality of transistors each having a gate insulation film formed on the well, a gate electrode formed on the gate insulation film and a pair of diffusion layers formed in the well; and an outer diffusion layer of the same conductivity type as that of the well and self-aligned with each of the diffusion layers in an outer periphery thereof within the well; the outer diffusion layer having an impurity concentration sufficient to provide a desired junction withstand voltage and having substantially the same width as that of a depletion layer to be generated when an operational voltage is applied to the corresponding transistor; the impurity of the well being set for a concentration such that a threshold voltage of a parasitic transistor appearing below the gate electrode connecting adjacent transistors is higher than a power suppl
    Type: Grant
    Filed: March 26, 1997
    Date of Patent: April 6, 1999
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masahiro Hasegawa, Junichi Tanimoto