Abstract: An automatic protocol synthesizing system in which, incomplete state transition diagrams of at least two functionally incomplete processes forming a protocol are received and completed state transition diagrams of the processes are outputted. In accordance with the present invention, there is provided a checking circuit for making a check for a logical error of the incomplete state transition diagram an embedding circuit embeds the state transition diagram of a process corresponding to the incomplete state transition diagram of an ith (where 1.ltoreq.i.ltoreq.N) one of the processes in the ith incomplete state transition diagram.