Abstract: A process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device includes the sequential formation of a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer using an in-situ deposition process in which the silicon nitride layer is not exposed to ambient atmosphere prior to the formation of the top oxide layer. To avoid exposure to ambient atmosphere, the first silicon oxide layer, the silicon nitride layer and the second silicon oxide layer are sequentially formed using either a PECVD or a SACVD process.

Abstract: In a method of manufacturing a semiconductor device, after a lateral growth region 107 is formed by using a catalytic element 105 for facilitating crystallization of silicon, the catalytic element is gettered into a phosphorus added region 108 by a heat treatment. Thereafter, a gate insulating film 113 is formed to cover active layers 110 to 112 formed, and in this state, a thermal oxidation step is carried out. By this, the characteristics of an interface between the active layers and the gate insulating film can be improved while abnormal growth of a metal oxide is prevented.

Abstract: A trench or a recess is formed in a predetermined part of a semiconductor substrate. Then, on the side of the trench or recess, a gate with a sidewall is formed by respective etching-back processes. Using the gate as a mask, a low concentration region for the LDD structure is formed. Using the gate and sidewall as a mask, a source region and a drain region are formed. Thus, the channel region makes a right angle with the trench or recess, and the channel region is bent. Further, the channel region is made to be formed so as to be longer than the width of the gate. Since the low concentration region for the LDD structure is formed only in the drain region, the source resistance can be decreased, and a gate with a narrow width can be easily formed. Further, even if the channel length is short, the occurrence of the DIBL phenomenon can be suppressed.

Abstract: A method for manufacturing a thin-film crystalline solar cell includes the steps of (i) forming a porous layer including a large number of fine pores in a surface portion of a crystalline substrate, (ii) transforming a part of the porous layer including the surface thereof into a smooth layer which does not include fine pores by providing the porous layer with excitation energy, and (iii) peeling the smooth layer from the substrate. The excitation energy is provided, for example, by performing heat treatment in a hydrogen atmosphere, irradiating with light having a wavelength equal to or less than 600 nm, or irradiating with an electron beam. It is thereby possible to form a thin-film crystalline semiconductor layer on an inexpensive and flexible substrate by simple processes.

Abstract: A method of making semiconductor devices with contacts protruding from openings in a passivation layer over an active chip area. Inside each opening, a relatively hard barrier layer is provided and a flash-plated film is applied to subsequently form a relatively soft diffusion barrier layer when a protruding contact is formed. Two semiconductor devices with electrodes are joined by embedding relatively hard electrodes of a first device into relatively soft electrodes of a second device. A reducing agent can be incorporated into an insulating resin applied between semiconductor chips at areas other than the bonded electrodes.

Abstract: A wafer planarization process which utilizes combined high density plasma chemical vapor deposition (HDP-CVD) process and chemical mechanical polishing (CMP) process is disclosed. This process includes the steps of (a) forming a first HDP-CVD layer on the surface of a semiconductor wafer using a first HDP-CVD composition having a higher etching/depositing component ratio and thus a lower CMP removal rate; (b) forming a second HDP-CVD layer on the first HDP-CVD layer using the same HDP-CVD process but with a second HDP-CVD composition having a lower etching/depositing component ratio and thus a higher CMP removal rate; and (c) using a chemical mechanical process to remove at least a part of the second HDP-CVD layer using the first HDP-CVD layer as a stopper. A protective layer with the same etching/deposition components but a different ratio than the sacrificial layer can be deposited on the sacrificial layer to minimize the dishing effect during the initial stage of the chemical mechanical polishing process.

Abstract: After formation of a sandwich over a substrate of a layer of silicon dioxide (3) followed by a layer of silicon (1) having a pad oxide (7) thereon and a patterned silicon nitride layer (9) over the pad oxide, the unmasked portion of the pad oxide and silicon are removed to provide mesas of silicon with silicon nitride thereover and possibly removal of some of the buried oxide layer. A flowable insulator (15), preferably silsesquioxane (H.sub.x SiO.sub.1.5, where x.ltoreq.1, depending upon the level of polymerization) in a contaminant-free, high purity solvent which is later removed during an annealing step, is placed over the exposed surface such that it fills the voids between the mesas of silicon with silicon nitride thereon and extends over the nitride. The flowable insulator, due to its flowability, provides a generally planar surface. The flowable insulator is etched back and a cap oxide (17) is optionally deposited over the etched back insulator layer.

Abstract: A transfer printing medium comprising a substrate supporting a thermal transfer dye and a radiation absorber positioned to provide thermal energy to the transfer dye when subjected to radiation within a predetermined absorption waveband, has a radiation absorber which is an infra-red absorbing poly(substituted)phthalocyanine compound in which each of at least five of the peripheral carbon atoms in the 1, 4, 5, 8, 9, 12, 13 or 16 positions (the "3,6-positions") of the phthalocyanine nucleus, as shown in Formula I, is linked by an atom from Group VB or Group VIB of the Periodic Table, other than oxygen, to a carbon atom of an organic radical. In preferred compounds each of the eight 3,6-positions is linked by an atom from Group VB or Group VIB, especially sulphur, selenium or nitrogen, to an organic radical.