Abstract: A process for forming a uniform nanoporous dielectric film on a substrate. The process includes horizontally positioning a flat substrate within a cup; depositing a liquid alkoxysilane composition onto the substrate surface; covering the cup such that the substrate is enclosed therein; spinning the covered cup and spreading the alkoxysilane composition evenly on the substrate surface; exposing the alkoxysilane composition to water vapor and base vapor to thereby form a gel; and then curing the gel. The invention also provides an apparatus for spin depositing a liquid coating onto a substrate. The apparatus has a cylindrical cup with an open top section and removable cover which closes the top. A vapor injection port extends through the center of the cover. Suitable means hold a substrate centered within the cup and spin the cup.

Abstract: A semiconductor device manufacturing method and a semiconductor device whereby alignment accuracy of a lower-layer pattern and an upper-layer pattern in a photolithography process may be improved. There are provided a pair of box marks for measuring the relative position between a lower-layer pattern and an upper-layer pattern of a semiconductor device in a box mark formation region. Since one box mark of the pair of box marks includes an opening groove 9-a formed on an interlayer insulating film 7 and a slit 9-b with a rectangular shape having a center roughly the same as the center of the opening groove 9-a, while the other box mark of the pair of box marks is an alignment mark 11-a formed on the opening groove, it is possible to suppress the change in shape of the edge part of the opening groove 9-a to a minimum even if reflow occurs again in the interlayer insulating film 7.

Abstract: A semiconductor device having lead terminals bent in a J-shape is disclosed. A radiating plate having a recess formed on an outer peripheral portion thereof is exposed to a lower face of a resin member and free ends of outer portions of the lead terminals are positioned in the recess of the radiating plate. The free ends of the outer portions of the lead terminals and the recess of the radiating plate are isolated from each other by projections of the resin member. Since the radiating plate is exposed to the lower face of the resin member, the heat radiating property is high whereas the radiating plate and the lead terminals are not short-circuited to each other at all.

Abstract: An electronic part in which a chip 2 having bump electrodes is sealed in a cavity 14 of a resin container 10, wherein the resin container having: a mounting board 1 having a conductor pattern 4 for bump-mounting the chip 2; an intermediate board 5 overlaid on the mounting board 1 and having a window for forming an inner wall apart from the chip 2 for predetermined distances; a cover board overlaid on the intermediate board 5 to cover the window; a first adhesive layer 8 which is interposed between overlaid portions of the mounting board 1 and the intermediate board 5; and a second adhesive layer 9 which is interposed between overlaid portion of the intermediate board 5 and the cover board 7, wherein the first and second adhesive layers 8 and 9 between which the intermediate board 5 is interposed are heated and pressed at a time in a direction of the thickness of each of the mounting board 1 and the cover board 7, and the mounting board 1, the intermediate board 5 and the cover board 7 are brought into intimat

Abstract: Described herein is a method for producing a haze-free (Ba, Sr)TiO3 (BST) film, and devices incorporating the same. In one embodiment, the BST film is made haze-free by depositing the film with a substantially uniform desired crystal orientation, for example, (100), preferably by forming the film by metal-organic chemical vapor deposition at a temperature greater than about 580° C. at a rate of less than about 80 Å/min, to result in a film having about 50 to 53.5 atomic percent titanium. In another embodiment, where the BST film serves as a capacitor for a DRAM memory cell, a desired {100} orientation is induced by depositing the bottom electrode over a nucleation layer of NiO, which gives the bottom electrode a preferential {100} orientation. BST is then grown over the {100} oriented bottom electrode also with a {100} orientation.

Abstract: A method for forming semiconductor devices is disclosed. The method of the present invention includes providing a semiconductor substrate, followed by forming shallow trench isolation (STI) process, and then a dummy gate is formed by silicon nitride layer which is deposited and defined. With appropriate wet etching, this dummy poly can be removed. After local punch-through implantation, reverse offset spacer is formed to reduce Cgd (capacitance is between gate and drain) and poly-CD (critical dimension). Polysilicon is deposited followed by polysilicon CMP. After thick Ti-salicidation, the usual CMOS (Complementary Metal-Oxide-Semiconductor) processes are proceeded.

Abstract: A process of fabricating a semiconductor device which has a wiring layer and active elements on a semiconductor substrate, the wiring layer and the active elements being protected by a protective film, and is provided with a projected electrode for connection with a outside in an opening portion of the protective film on an Al electrode pad electrically connected to the wiring layer, which comprises the steps of: removing by sputtering a surface oxide film formed on a surface of the Al electrode pad; depositing a film of a first metal on the Al electrode pad by substituting the first metal with Al constituting the Al electrode pad; and depositing a film of a second metal for constituting the projected electrode on the film of the first metal by substituting the first metal with the second metal, and forming the projected electrode by electroless plating by use of autocatalytic reaction.

Abstract: The present invention is an improved semiconductor device and an improved method of manufacturing a semiconductor device. The present invention deposits a layer of oxynitride where gate oxidation would normally take place. Alternatively, the method according to the present invention uses a plurality of layers of dielectric material where gate oxidation would normally take place including a layer of oxynitride having a nitrogen content. The layer of oxynitride is deposited under a predetermined pressure using a stream of gas, wherein insensitivity to defects on a surface of the substrate results from the oxynitride layer.

Abstract: A method for removing a multiplicity of solder bodies connected to a semiconductor wafer through a copper wetting layer from the semiconductor wafer is disclosed. In the method, a semiconductor wafer that has on a top surface a multiplicity of solder bodies electrically connected to a multiplicity of bond pads through a multiplicity of copper wetting layers is first provided. When the multiplicity of solder bodies is found out of specification or must be removed for any other quality reasons, the semiconductor wafer is exposed to an etchant that has an etch rate toward the copper wetting layer at least 5 times the etch rate toward a metal that forms the multiplicity of bond pads. The semiconductor wafer may be removed from the etchant when the multiplicity of copper wetting layers is substantially dissolved such that the multiplicity of solder bodies is separated from the multiplicity of bond pads. The multiplicity of solder bodies may be either solder bumps or solder balls.

Abstract: A process for fabricating a MOSFET device, featuring source/drain extension regions, formed after the utilization of high temperature processes, such as heavily doped source/drain regions, has been developed. Disposable insulator spacers are formed on the sides of doped, SEG silicon regions, followed formation of a gate insulator layer, and an overlying gate structure, on a region of the semiconductor substrate located between the doped SEG silicon regions. The temperature experienced during these process steps result in the formation of the heavily doped source/drain, underlying the SEG silicon regions. Selective removal of the disposable spacers, allows the source/drain extension regions to be placed in the space vacated by the disposable spacers, adjacent to the heavily doped source/drain region. Insulator spacers are then used to fill the spaces vacated by removal of the disposable spacers, directly overlying the source/drain extension regions.

Abstract: A method of fabricating a semiconductor device on a semiconductor wafer of the type having a plurality of active layers that includes the steps forming a layout for at least one of the active layers where the layout contains a plurality of active region segments and a plurality of inactive regions. The layout is then modified by adding a plurality of dummy active segments in the inactive regions. The layout is further modified by removing a plurality of sub-regions from the active regions to form a plurality of sub-inactive regions. The semiconductor wafer is then processed using the modified layout to provide an environment during the processing of the active layer wherein the relative area of the active to the inactive regions is substantially equal across the wafer.

Abstract: A chip carrier and lid are sealed by mounting the chip carrier in an inverted position and mounting a lid having a sealing preform in an inverted position beneath and facing the chip carrier. The chip carrier and lid are then heated to melt the sealing preform and the chip carrier and lid are moved together to join them at the sealing preform.

Abstract: A method to reduce via poisoning in low-k copper dual damascene interconnects through ultraviolet (UV) irradiation of the damascene structure is disclosed. This is accomplished by irradiating the insulative layers each time the layers are etched to form a portion of the damascene structure. Thus, irradiation is performed once after the forming of a trench or a via, and again for the second time when the insulative layers are etched to form the remaining trench or via. The trench and hole openings of the dual damascene structure are exposed to UV light in a dry ozone environment, which then favorably alters the surface characteristics of the low-k dielectric walls which are normally hydrophobic. Hence, during etching, moisture is not absorbed into the walls.

Abstract: Silicon-on-insulator (SOI) islands are formed in a silicon substrate. A first set of trenches is formed in the silicon substrate, leaving laterally-isolated rows of silicon between the trenches. The first set of trenches is then filled with silicon oxide. A second set of trenches is then formed in the silicon substrate at a direction orthogonal to the first set of trenches. Silicon nitride is then deposited over the sidewalls of the second set of trenches. An isotropic chemical etch is then used to fully undercut narrow the laterally-isolated rows of silicon between the second set of trenches to form evacuated regions beneath silicon islands. A subsequent oxidation step fills the evacuated regions to form the SOI islands.

Abstract: A circuit isolation technique that uses implanted ions in embedded portions of a wafer substrate to lower the resistance of the substrate under circuits formed on the wafer or portions of circuits formed on the wafer to prevent the flow of injected currents across the substrate. The embedded ions provide low resistance regions that allow injected currents from a circuit to flow directly to a ground potential in the same circuit rather than flowing across the substrate to other circuits. High energy implantation processes on the order of 1 MeV to 3 MeVs can be used to implant the ions in embedded regions. Multiple energy levels can be used to provide thick embedded layers either prior to or after application of an epitaxial layer. Various masking materials can be used to mask the isolation regions during the implantation process, including hard masking materials such as silicon dioxide or silicon nitride, poly-silicon or an amorphous silicon layer, and a photoresist layer.

Abstract: Methods of forming dielectric layers and methods of forming capacitors are described. In one embodiment, a substrate is placed within a chemical vapor deposition reactor. In the presence of activated fluorine, a dielectric layer is chemical vapor deposited over the substrate and comprises fluorine from the activated fluorine. In another embodiment, a fluorine-comprising material is formed over at least a portion of an internal surface of the reactor. Subsequently, a dielectric layer is chemical vapor deposited over the substrate. During deposition, at least some of the fluorine-comprising material is dislodged from the surface portion and incorporated in the dielectric layer. In another embodiment, the internal surface of the reactor is treated with a gas plasma generated from a source gas comprising fluorine, sufficient to leave some residual fluorine thereover.

Abstract: A process for fabricating a VLSI device comprising trench isolation regions. The trench isolation regions of a VLSI device is fabricated by a process comprising the following steps: Depositing and patterning pad layers on a substrate to form active regions separated from pad-layer-covered regions; forming side walls at each active region to cover portions of the active region other than its central portion; depositing a first oxide at the space surrounded by the side walls and the central portion of the active region; removing the side walls to form trenches at the active region; and depositing a second oxide on the substrate to fill the trenches and cover the first oxide, the second oxide and the first oxide together forming an oxide trench isolation region.

Abstract: A method for fabricating an electric double-layer capacitor includes the steps of contacting a polarized electrode which includes a polymer having no bridge structure therein and activated carbon and a collector which includes a polymer and conductive additives, exposing the polarized electrode and the collector to electron beam to form a bridge structure therebetween. The electric double-layer capacitor having the polarized electrode and the collector thus formed has a low equivalent serial resistance and can be manufactured with a higher throughput.

Abstract: Process and separating means for the production of a thin film solar module (10) comprising a plurality of solar cells (11) arranged side-by-side on a common substrate (12), which are produced by employing a plurality of layer deposition steps and layer separating steps during the course of cell production and which are electrically interconnected with one another, wherein after the application of a first contact layer (14) on substrate (12) and the cell-wise separation thereof a pn double layer (16) is applied on a contact layer and, thereafter, is mechanically separated in that a scraping cutting tool serving as separating means scrapes, by a relative movement to the coated substrate, a cell structure into said pn double layer, wherein said cutting tool slides, preferably without being raised or rotated, with a plane sliding surface of a flattened tip on said first contact layer (14) which has a higher hardness than said pn double layer (16).

Abstract: A method for establishing conditions of making an index representing characteristics of a MOSFET in a permitted range by means of differentially injecting ions into a wafer. The method includes the steps of: making a curve indicating an amount of energy contamination with respect to a junction depth, and determining a permitted amount of energy contamination with respect to a desired junction depth. A MOSFET having substantially no deterioration of the characteristics can be obtained by referring to the curve, and establishing a degree of vacuum of and/or a distance of a beam line.