Abstract: An image processing device includes a frame buffer, a first display engine, a clock signal generator, a spread spectrum clock generator, a first-in-first-out (FIFO) buffer and a reset signal generator. The FIFO buffer receives and stores the pixel digital data from the first display engine according to a data writing index controlled by a working clock signal from the clock signal generator and outputs the pixel digital data to the planar display according to a data reading index controlled by a spread spectrum clock signal from the spread spectrum clock generator. The reset signal generator receives and checks the pixel digital data and generates a reset signal to the FIFO buffer to reset the data writing index and the data reading index when one of the pixel digital data to be inputted into the FIFO buffer is consistent with a preset condition.