Abstract: In one embodiment, techniques are disclosed for causing a programmable processor to process one instruction at a time. Single-step debugging may be performed by taking an exception after each instruction or by invoking emulation mode after each instruction. The particular single-step debugging technique may be based upon state of control bits, or may be based upon the processor's current mode of operation, or both.

Abstract: An apparatus and method for implementing a switch instruction in the IA64 architecture is provided. With the apparatus and method, a first register is used to identify whether a low is either 0, 1 or some other value, and a second register is used to identify a shift amount. The first register is then shifted by the shift amount in the second register. The first register value is then moved to the predicate register set in the IA64 architecture, thereby identifying which branch is to be taken. If the first register is shifted outside the predicate registers, a default address is provided.

Abstract: An exception handler for a processor is split into two functional units to permit exceptions to be classified into two categories. The first category of exceptions includes performance critical excepted instructions, while the second category includes non-performance critical excepted instructions. The performance critical exceptions are routed to a speculative exception handler, which resolves the exceptions speculatively, even though the excepted instruction may lie in a speculative path of the program flow. The non-performance critical exceptions are routed to a non-speculative exception handler that only resolves exceptions when the excepted instruction is certain to execute in an actual path of the program flow.

Abstract: An apparatus and method for externally managing data within an asynchronous pipeline. The asynchronous pipeline over which control is sought includes a data path and a control path. In accordance with the method of the present invention, a data tag value is assigned to the data prior to its entry into the asynchronous pipeline. The data tag value is sent into the control path at the same time the data is sent into its data path such that the data tag value passes through the asynchronous pipeline in parallel with the data to which it is assigned. At a given stage within the asynchronous pipeline, the data tag value is compared with a control tag value, and only in response to the data tag value matching the control tag value is the data permitted to pass to the next stage within the asynchronous pipeline.

Abstract: A method of performing link stack operations comprises the steps of reading and writing to a link stack. During a write, a location in the link stack pointed to by a current write pointer is selected and a link address associated with an instruction and a current read pointer to the link stack are written into the selected location. After the write operation, the read pointer is updated such that the new read pointer equals the current write pointer and the write pointer is updated. During a read from the link stack, a location in the link stack is selected using a current read pointer. A new read pointer and a link address associated with an instruction are read from the selected read location.

Abstract: An apparatus and method for selecting a next available buffer from among an array of buffers using a reduced count of logic gates. The apparatus includes an array of computational cells coupled to one another in a cascaded fashion, wherein each computational cell corresponds to a respective buffer in the array of buffers. The array of computational cells includes a first set of inputs for receiving data in accord with an availability vector comprising 1 bit for each buffer that identifies which buffers are available for allocation. A second set of inputs in accord with a current selected entry vector is also provided, wherein the current selected entry vector includes a single asserted bit that identifies that last buffer to be allocated. A computational cell includes logic to implement a pair of predefined logic equations, whereby a next available vector in accord with a first set of outputs on the array of computational cells.

Abstract: A find-instructions-and-allocate-ports (FIAP) circuit and method are provided for quickly and efficiently locating one or more instructions that are ready for execution during a launch cycle in an out of order processor and allocating one or more ports associated with one or more execution resources to such ready instructions during the launch cycle. In architecture, the processor includes an instruction reordering mechanism, for example, a queue, having a plurality of slots for temporarily storing a plurality of respective instructions. Instructions can be executed in an out of order sequence from the queue. Each slot is provided with the FIAP circuit for causing and preventing launching, when appropriate, of their respective instruction. A plurality of signals is propagated successively through the FIAP circuits of the queue that causes the queue to launch a predefined plurality of the instructions, which corresponds to a predefined plurality of ports associated with the one or more execution resources.

Abstract: Described is a data processing system and processor that provides full multiprocessor speculation by which all instructions subsequent to barrier operations in a instruction sequence are speculatively executed before the barrier operation completes on the system bus. The processor comprises a load/store unit (LSU) with a barrier operation (BOP) controller that permits load instructions subsequent to syncs in an instruction sequence to be speculatively issued prior to the return of the sync acknowledgment. Data returned is immediately forwarded to the processor's execution units. The returned data and results of subsequent operations are held temporarily in rename registers. A multiprocessor speculation flag is set in the corresponding rename registers to indicate that the value is “barrier” speculative. When a barrier acknowledge is received by the BOP controller, the flag(s) of the corresponding rename register(s) are reset.

Abstract: In one embodiment, a method for speculatively reusing regions of code includes identifying a reuse region and a data input to the reuse region, determining whether a data output of the reuse region is contained within reuse region instance information pertaining to a plurality of instances of the reuse region, and when the data output is not contained within the reuse region instance information, predicting the data output of the reuse region based on the reuse region instance information.

Abstract: A unified buffer, comprising a shifting queue, receives instructions to be tracked by receiving units in a computer architecture. The receiving units search the unified buffer from the oldest entry to the most recent entry. Status bits in each entry indicate which of the receiving unit(s) the entry is destined for. Existing entries in the unified buffer shift down when a new entry is inserted at the top. Entries may be passed to different receiving units by updating the status bits; and an entry expires after it has been accepted by its final receiving unit.

Abstract: A method and apparatus are provided for improving the rate at which macroinstructions are transformed into corresponding microinstructions. Encoding is added to a microcode storage device. The encoding indicates that a microinstruction flow will end in a determined number of cycles. The number of cycles is determined by the number of canceled instructions in a processing pipeline that would be introduced if no flow length prediction was used. For flow lengths less than a determined number of cycles, a hint bit is used in an entry point structure. For flow lengths greater than a determined length, a hint bit is encoded at a third line from an end of the microinstruction flow. Using this method, flows of any length can be hinted. Furthermore, flows that do not originate from the entry point structure can also be hinted. The method reduces the number of hint bits that are needed in the entry point structure and provides for better prediction.

Abstract: To make a branch prediction, a branch prediction apparatus determines a trigger load instruction whose value feeds into the branch instruction. A hash value is associated with the branch instruction. The branch prediction apparatus computes the hash value based on the trigger load instruction. If the hash value has not changed, the branch prediction apparatus predicts the branch to be chosen based on past predictions for the hash value.

Abstract: One embodiment of the present invention provides a system that prefetches from memory by using an assist processor that performs data speculation and that executes in advance of a primary processor. The system operates by executing executable code on the primary processor while simultaneously executing a reduced version of the executable code on the assist processor. This allows the assist processor to generate the same pattern of memory references that the primary processor generates in advance of when the primary processor generates the memory references. While executing the reduced version of the executable code, the system predicts a data value returned by a long latency operation within the executable code. The system subsequently uses the predicted data value to continue executing the reduced version of the executable code without having to wait for the long latency operation to complete.

Abstract: A system and method for recovering from mispredicted paths in pipelined computer architectures. Targets within an instruction window exhibit spatial locality. To exploit this property, a mechanism detects the branch target within the instruction window. A second process eliminates the need for full renaming and re-execution of mispredicted paths by handling a dependency chain of instructions.

Abstract: A simultaneous and redundantly threaded, pipelined processor can execute the same set of instructions simultaneously as two separate threads to provide, for example, fault tolerance. One thread is processed ahead of the other thread thereby creating a “slack” between the two threads so that the instructions in one thread are processed through the processor's pipeline ahead of the corresponding instructions from the other thread. The thread, whose instructions are processed earlier, is called the “leading” thread. The other thread is the “trailing” thread. By setting the amount of slack appropriately, all or at least some of the cache misses or branch misspeculations encountered by the trailing thread can be resolved by the time the corresponding instructions from the trailing thread are fetched and processed through the pipeline. The invention, therefore, improves the performance of a fault tolerant, simultaneous and redundantly threaded processor.

Abstract: When a branch instruction for awaiting an event is detected in an information processing apparatus which performs a pipeline process including a branch prediction, a branch prediction for the branch instruction is suppressed. As a result, a prefetch operation for an instruction subsequent to the branch instruction is promoted, and the subsequent instruction is immediately executed when the event to be awaited occurs.

Abstract: A method and apparatus to allow program steps in an issue queue to be sent to the execution queue in a non program order provides reduced stall by allowing out of program order steps to be executed as needed resources become available. The method uses a modulus operation to preassign locations in the execution queues, and keep the entries in proper program order. The method employs an additional bit to represent the modules result (valve) and may also utilize a load store number mapping memory to increase execution speed. With such an arrangement a computer system may decrease the lost performance due to waiting for required resource (i.e., memory or bus) availability for the current instruction, by issuing instructions for which the memory or bus resource is available even though the instruction is not the next one in the original program order. Thus the present invention allows memory reference instructions to issue as resources are available.

Abstract: An indirect branch predictor includes a buffer storing branch target addresses corresponding to previously executed indirect branch instructions. The buffer is indexed with an index derived from history information corresponding to previously predicted indirect branch instructions and from the PC of the particular indirect branch instruction being predicted. In one embodiment, the buffer may be tagless and/or direct mapped. In various embodiments, the indirect branch target predictor may generate the index to the buffer using one or more techniques to improve the accuracy of the prediction: (i) offsetting the history information from the various previously predicted indirect branch instructions; (ii) weighting the history information based on the age of the previously predicted indirect branch instructions; and/or (iii) reversing the bit order of the PC of the particular indirect branch instruction being predicted.

Abstract: An indirect branch predictor includes a buffer storing branch target addresses corresponding to previously executed indirect branch instructions. The buffer is indexed with an index derived from history information corresponding to previously predicted indirect branch instructions and from the PC of the particular indirect branch instruction being predicted. In one embodiment, the buffer may be tagless and/or direct mapped. In various embodiments, the indirect branch target predictor may generate the index to the buffer using one or more techniques to improve the accuracy of the prediction: (i) offsetting the history information from the various previously predicted indirect branch instructions; (ii) weighting the history information based on the age of the previously predicted indirect branch instructions; and/or (iii) reversing the bit order of the PC of the particular indirect branch instruction being predicted.

Abstract: An apparatus for and a method of ensuring that a non-speculative instruction is not fetched into an execution pipeline, where the non-speculative instruction, if fetched, may cause a cache miss that causes potentially catastrophic speculative processing, e.g., speculative transfer of data from an I/O device. When a non-speculative instruction is scheduled for a fetch into the pipeline, a translation lookaside buffer (TLB) miss is made to occur, e.g., by preventing the lowest level TLB from storing any page table entry (PTE) associated with any of the non-speculative instructions. The TLB miss prevents the occurrence of any cache miss, and causes a micro-fault to be injected into the pipeline. The micro-fault includes an address corresponding to the subject non-speculative instruction, and when it reaches the end of the pipeline, causes a redirect of instruction flow of the pipeline to the address, and thus the non-speculative instruction is fetched and executed in a non-speculative manner.