Abstract: A method of fabricating a semiconductor structure utilizing doped silicate glass on a substrate of a wafer. The method includes the step forming a modulation doped silicate glass structure over a first layer of the wafer. The modulation doped silicate glass structure is formed by depositing at least two alternating layers of heavily-doped silicate glass and lightly-doped silicate glass over the first layer. Both the heavily-doped silicate glass and lightly-doped silicate glass layers may comprise glass doped with both a first dopant and a second dopant. The first dopant may represent, for example, phosphorous, and the second dopant may represent, for example, boron.

Abstract: A semiconductor device includes a heat generating element disposed on a front surface of a semiconductor substrate and a cavity disposed within the semiconductor substrate opposite the heat generating element. In this structure, heat generated by the heat generating element is conducted through the substrate to the cavity, whereby the thermal conductivity of the device is improved. In a method for producing the semiconductor device, portions of the substrate at opposite sides of the heat generating element are selectively etched in a direction perpendicular to the front surface to form first holes (first etching process). Thereafter, the substrate is selectively etched from the front surface to form second holes beneath the respective first holes (second etching process). During the second etching process, the second holes are connected to each other, resulting in the cavity for heat radiation.

Abstract: A low threshold voltage power DMOS transistor structure is disclosed having a lightly doped channel region formed in a shallow layer of relatively lightly doped epitaxial silicon. The light doping of the shallow epitaxial layer minimizes variations in threshold voltage and local variations in punch-through susceptibility due to nonuniformities in epitaxial doping concentration. A relatively heavily doped epitaxial layer is disposed underneath the shallow lightly doped epitaxial layer to reduce the drain to source resistance, R.sub.DS. Because the relatively heavily doped epitaxial layer is located below the channel region and not in the regions of the structure most susceptible to body region punch-through, providing the relatively highly doped epitaxial layer does not cause variations in threshold voltage and does not cause variations in the reverse bias voltage at which punch-through across the body region occurs.

Abstract: A method of manufacturing a device whereby a layer structure with semiconductor elements and conductor tracks is formed on a first side of a semiconductor wafer which is provided with a layer of semiconductor material disposed on an insulating layer. Then the semiconductor wafer is fastened with said first side to a support wafer by means of a glue layer, the support wafer being provided with a metallization. Material is then removed from the semiconductor wafer from the other, second side thereof until the insulating layer is exposed. Contact windows are provided in the insulating layer from the first side of the semiconductor wafer before the latter is refastened on the support wafer. These windows are filled with a material which can be removed selectively relative to the insulating layer. The contact windows are opened from the second side of the semiconductor wafer after the latter has been fastened on the support wafer and after the insulating layer has been exposed.

Abstract: A method of forming a capacitor on a semiconductor substrate includes forming a first oxide layer on the semiconductor substrate. A contact hole is then formed in the first oxide layer. A first conductive layer is formed on the first oxide layer and in the contact hole. Then the first conductive layer is etched to form a node structure. A non-conformal oxide is formed on the node structure so that the non-conformal oxide has an overhang portion and a lower portion on the sidewall of the node structure. The non-conformal oxide is isotropically etched to remove the lower portion of the non-conformal oxide and to expose the lower sidewall of the node structure. A second conductive layer is conformally deposited on the non-conformal oxide layer and the lower sidewall of the node structure. The second conductive layer is anisotropically etched, using the overhang portion of the non-conformal oxide as a mask. Then the non-conformal oxide is removed by using a highly selective etching process.

Abstract: A fabrication method of a compound semiconductor FET that enables to produce source/drain electrodes and a gate electrode at any positions flexibly without increase of the number of necessary process steps. First, a compound semiconductor substructure having on its surface first regions on which source/drain electrodes are formed respectively and a second region on which a gate electrode is formed is prepared. A patterned mask film is then formed on the surface of the substructure. The mask film has first windows for the source/drain electrodes and a second window for the gate electrode. A conductor film is selectively formed on the surface of the substructure using the patterned mask film as a mask. The conductor film contains first parts placed on the first regions through the respective first windows of the mask film and second part placed on the second region through the second window of the mask film.

Abstract: A crystalline silicon thin film transistor having an LDD (lightly doped drain) structure and a process for fabricating the same, which comprises establishing an LDD by forming a gate insulating film and a gate electrode on an island-like semiconductor region and implanting thereafter impurities in a self-aligned manner to establish an LDD, anodically oxidizing the gate electrode and introducing impurities to form source and drain regions, partially or wholly removing the anodic oxide from the surface of the island-like semiconductor region to expose the LDD region, and irradiating a laser beam or an intense light having an intensity equivalent to that of the laser beam to activate the impurity region inclusive of the LDD.

Abstract: On a silicon substrate in which boron (B) has been introduced, an n.sup.+ polysilicon film and a tungsten silicide film are sequentially deposited, with a gate oxide film being interposed between the substrate and the polysilicon film, to form a gate electrode. A sidewall of p.sup.+ polysilicon is formed at each side of said gate electrode. A source/drain diffusion layer of an n.sup.+ region is self-aligned with a side edge portion of the gate electrode including the sidewall. The formation of the sidewall is performed after the source/drain diffusion layers have been formed using a dummy sidewall. The gate structure thus formed has a steep potential gradient in the lateral direction of channel region. In the field effect transistor thus formed, the short channel effect is efficiently suppressed.

Abstract: Integrated circuit fabrication with a thin layer of oxynitride atop the interlevel dielectric, to provide an etch stop to withstand the overetch of the metal layer.

Abstract: A plasma etch method for patterning for use within an integrated circuit a blanket conductor layer such that an integrated circuit layer adjoining the blanket conductor layer is not damaged when the blanket conductor layer is patterned to form a patterned conductor layer through the plasma etch method. There is first provided a semiconductor substrate. There is then formed over the semiconductor substrate a blanket conductor layer, where the blanket conductor layer communicates electrically with the semiconductor substrate in a fashion such that an electrical charge is shunted from the blanket conductor layer into the semiconductor substrate when the blanket conductor layer is patterned to form the patterned conductor layer through the plasma etch method. There is then patterned through the plasma etch method the blanket conductor layer to form the patterned conductor layer.

Abstract: A thin film transistor and a fabricating method for a thin film transistor is disclosed which may be suitable for memory cells of a static random access memory (SRAM) or other devices. A thin film transistor according to this invention may include an insulation substrate, a gate electrode formed to have a negative slope at one side thereof on the insulation substrate, an insulation film side wall formed at the other side of the gate electrode, a gate insulation film formed on the insulation substrate, gate electrode and side wall, a semiconductor layer formed on the gate insulation film, impurity diffusion regions selectively formed within the semiconductor layer over the gate electrode, the side wall and the insulation substrate on the other side of the gate electrode, and a channel region formed within the semiconductor layer at the side of the gate electrode having the negative slope.

Abstract: A method for forming a polycrystalline semiconductor thin film according to the present invention includes the steps of: forming a semiconductor thin film partially containing microcrystals serving as crystal nuclei for polycrystallization on an insulating substrate; and polycrystallizing the semiconductor thin film by laser annealing.

Abstract: An illumination source comprising a porous silicon having a source of electrons on the surface and/or interticies thereof having a total porosity in the range of from about 50 v/o to about 90 v/o. Also disclosed are a tritiated porous silicon and a photovoltaic device and an illumination source of tritiated porous silicon.

Abstract: A method for forming within an integrated circuit a low impurity diffusion polysilicon layer. Formed upon a semiconductor substrate is an amorphous silicon layer. Formed also upon the semiconductor substrate and contacting the amorphous silicon layer is a polysilicon layer. The amorphous silicon layer and the polysilicon layer are then simultaneously annealed to form a low impurity diffusion polysilicon layer. The low impurity diffusion polysilicon layer is a polysilicon multi-layer with grain boundary mis-matched polycrystalline properties. Optionally, a metal silicide layer may be formed upon the amorphous silicon layer and the polysilicon layer either prior to or subsequent to annealing the amorphous silicon layer and the polysilicon layer. The metal silicide layer and low impurity diffusion polysilicon layer may then be patterned to form a polycide gate electrode.

Abstract: A method for forming an interconnection pattern in a semiconductor device for reducing metallic reflection, includes the steps of forming a conductive layer on a substrate, polishing the conductive layer to form a rugged surface on the conductive layer, and selectively removing the polished conductive layer to form the interconnection pattern.

Abstract: A method of forming recesses in a substrate such as a capacitor so as to increase the surface area thereof and therefore the charge storage capacity of the capacitor. This is accomplished by utilizing a micro mask formed by agglomeration on the surface of the substrate. The agglomerated material, such as gold, titanium nitride or titanium silicide, is used as a mask for selectively etching the substrate to form recesses therein. Alternatively, an oxide transfer mask can be utilized with the agglomerated material micro mask to etch the substrate.

Abstract: A method for fabricating Thin Film Transistors includes the steps of forming a gate electrode on a substrate, forming a gate insulation film and a semiconductor layer successively on the substrate, forming a sidewall spacer only at one sidewall of the gate electrode on the semiconductor layer, and forming impurity regions in the semiconductor layer on both sidewalls of the gate electrode by ion-injecting impurity ions into the semiconductor layer.

Abstract: The uniformity in buried condition of conductors in contact holes is enhanced over the entire wafer surface. A first resist is coated on a conductor provided selectively in a contact hole formed in an insulating film provided on a semiconductor substrate, as well as on the insulating film, and a resultant structure is flattened. The first resist and the conductor are removed with their portions being left. A second resist is coated on the conductor and insulating film and a resultant structure is flattened. The second resist and the conductor are removed until the insulating film is exposed.

Abstract: An antifuse includes an antifuse material disposed between a lower conductive electrode and an upper conductive electrode. The antifuse material includes a layer of amorphous silicon disposed between two layers of silicon nitride. A thin layer of silicon dioxide is disposed between the layer of amorphous silicon and one of the silicon nitride layers.

Abstract: A method for making a semiconductor device, includes steps of: forming a lower wiring on a semiconductor substrate; forming layer insulation film to cover the lower wiring; coating a surface of the layer insulation film with organic or inorganic SOG to form SOG film; heat-treating the SOG film; etching the SOG film to even a surface of the SOG film; forming an aperture reaching through the SOG film and the layer insulation film to the lower wiring; and filling the aperture with a conductive material to form a through-hole, wherein the coating step with the organic or inorganic SOG is conducted in amine system gas atmosphere.