Abstract: The disclosure relates in some aspects to on-chip processing circuitry formed within the die of a non-volatile (NVM) array to perform data searches. In some aspects, the die includes components configured to sense wordlines of stored data in the NVM array by applying voltages on the wordlines serially, and then search for an input data pattern within the serially-sensed wordlines. In some examples, the components of the die include latches and circuits configured to perform bitwise latch logic search operations. In other examples, the search components are configured with under-the-array or next-to-the-array dedicated search circuitry that uses registers and/or random access memory (RAM). Other aspects relate to a separate controller device for controlling the on-chip NVM search operations. For example, the controller may determine whether to search for data using search components of the NVM die or processors of the controller based, e.g., on a degree of fragmentation of data.

Abstract: A distributed storage system including memory hosts and at least one curator in communication with the memory hosts. Each memory host has memory, and the curator manages striping of data across the memory hosts. In response to a memory access request by a client in communication with the memory hosts and the curator, the curator provides the client a file descriptor mapping data stripes and data stripe replications of a file on the memory hosts for remote direct memory access of the file on the memory hosts.

Abstract: An apparatus includes processing circuitry for performing data processing in response to instructions of a software execution environment. Configuration storage circuitry stores a set of memory transaction parameters in association with a partition identifier and configuration application circuitry applies the set of memory transaction parameters in respect of memory transactions issued by the software execution environment that identifies the partition identifier. The memory transaction parameters comprise a minimum target allocation of a resource used by a memory system in handling the memory transaction that identifies the partition identifier. Also provided is an apparatus that comprises processing circuitry for performing data processing in response to instructions of a software execution environment. Configuration storage circuitry stores a set of memory transaction parameters and associated partition identifiers.

Abstract: Methods, systems, and devices for in-memory associative processing for vectors are described. A device may perform a computational operation on a first set of contiguous bits of a first vector and a first set of contiguous bits of a second vector. The first sets of contiguous bits may be stored in a first plane of a memory die and the computational operation may be based on a truth table for the computational operation. The device may perform a second computational operation on a second set of contiguous bits of the first vector and a second set of contiguous bits of the second vector. The second sets of contiguous bits may be stored in a second plane of the memory die and the computational operation based on the truth table for the computational operation.

Abstract: A storage system has filtered views of data. The storage system receives a read request for a filtered view of data in memory. The read request is associated with one or more permissions for viewing the data. The storage system identifies a subset of the data, based on the one or more permissions. The storage system provides the filtered view. The filtered view includes the subset of the data.

Abstract: An information handling system includes a first memory device that provides a first system physical address (SPA) space for the information handling system having a first capacity. Data is stored on the first memory device with a first interleave configuration. A second memory device provides a second SPA space for the information handling system that has a second capacity that is greater than or equal to the first capacity. Without rebooting the information handling system and without halting a process, the system de-interleaves the data stored on the first memory device, stores the data on the second memory device, and re-interleaves the data.

Abstract: A method of operating an object-based storage system, practiced by the storage system, is provided. The method includes establishing a plurality of buckets for objects, in the storage system and establishing a plurality of bucket views in the storage system, each bucket view supporting access to objects of one of the plurality of buckets. The method includes accessing an object of a bucket through one of the plurality of bucket views.

Abstract: A method of data caching includes; determining a process corresponding to a read request communicated from a host, obtaining historical access information for the process according to historical process information stored in a cache, wherein the historical process information includes at least one of historical access information for the process and heat information for one or more regions historically accessed by the process, determining a first region historically accessed by the process according to the historical access information, such that heat information for the first region satisfies a first preset condition, and loading a physical address for the first region from a storage device to the cache.

Abstract: A storage device includes a non-volatile memory including a plurality of non-volatile memory cells, a buffer memory configured to temporarily store write data to be written to the non-volatile memory or read data read from the non-volatile memory, and a controller configured to receive a sleep mode signal from an external host. When the sleep mode signal is received by the controller, the controller is configured to block a first power supplied to the non-volatile memory and set the buffer memory to one of a first mode in which a second power is blocked from being supplied to the buffer memory and a second mode in which the buffer memory operates with low power. The write data stored in the buffer memory is written to the non-volatile memory when the buffer memory is set to the first mode.

Abstract: An illustrative embodiment disclosed herein is an apparatus including a processor and a memory. In some embodiments, the memory includes programmed instructions that, when executed by the processor, cause the apparatus to upload an object to a source bucket in an object store and create a lambda bucket in the object store that is symlinked to the source bucket. In some embodiments, the lambda bucket is associated with a predefined transformation. In some embodiments, the memory includes the programmed instructions that, when executed by the processor, cause the apparatus to receive a request to download the object from the lambda bucket, detect that the object is in the source bucket, fetch the object from the source bucket, transform the object, by compute resources of the object store, using the predefined transformation, and download the transformed object.

Abstract: An air freight rate data caching method and system. The method includes converting air freight rate data into a data format of a first-level cache, and storing same in the first-level cache; performing, on the basis of a flight origin city and a flight destination city, data fragmentation on the air freight rate data stored in the first-level cache so as to generate fragmented data; and storing the fragmented data, after same is validated, in a second-level cache. Each data node of the fragmented data cached in the second-level cache only includes part of the air freight rate data on which a fragmentation algorithm can be performed, and therefore, the horizontal expansion capacity of a cache system is improved relative to the case where cached data copies are all complete sets.

Abstract: A drive subset matrix is created with at least N+1 drives each having N*N same-size subdivisions. Conceptually, N submatrices are created along with spares equivalent to at least one drive of storage capacity. The spares are located such that every drive has an equal number of spares +/?1. One protection group is located in a lowest indexed subdivision of each of the submatrices. Members of other protection groups are located by selecting members in round robin order and placing each selected member in a free subdivision having a lowest drive index and lowest subdivision index. The drive subset can be grown, split, and reorganized to restore balanced and efficient distribution of spares.

Abstract: According to one embodiment, a controller of a memory system calculates an amount of transferred data per unit time in response to completion of processing of a first I/O command. While the calculated amount of transferred data per unit time exceeds a first threshold, the controller does not transmit, to a host, a completion response indicating completion of the first I/O command. When the calculated amount of transferred data per unit time is equal to or less than the first threshold, the controller transmits, to the host, the completion response indicating the completion of the first I/O command.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to add one or more entries to a log file system (LFS) invalidation table and scan the LFS invalidation table during a storage optimization operation. Each entry of the one or more entries maps a new valid logical block address (LBA) to an old invalidated LBA. The new valid LBA is updated version of the old invalidated LBA. The storage optimization operation includes moving data from a first location to a second location.

Abstract: A method of caching mapping table for use in a flash memory device having a flash memory controller and a flash memory is provided. The method includes: in response to a host read command, determining whether a group of a logical-to-physical (L2P) required by handling the host read command has been loaded to a DRAM of the flash memory controller; if the required group of the L2P mapping table has not been loaded to the DRAM, loading the required group of the L2P mapping table from the flash memory to a SRAM of the flash memory controller; directly accessing the SRAM to obtain an L2P address associated with the host read command from the required group of the L2P mapping table; and performing a read operation on the flash memory in response to the host read command according to the obtained L2P address.

Abstract: The present invention discloses a memory access apparatus having address scrambling mechanism that includes an address scrambling circuit and a memory controller. The address scrambling circuit performs the steps outlined below. An original access address is received to be interpreted into original unit indexes and a minimal original unit according to regional unit levels of a memory. Scrambled unit indexes and a minimal scrambled unit are generated correspondingly according to a random address generation algorithm, to further generate a scrambled access address accordingly, in which when a plurality of different original access addresses have at least one the same original unit indexes from the highest block unit level, the scrambled unit indexes generated therefrom are the same. The memory controller accesses the memory according to the scrambled access address.

Abstract: The invention introduces a method for performing data writes into a flash memory, at least including the steps: determining whether at least one host write command that requires to process immediately is presented in a submission queue (SQ) before performing a portion of a Host-Flash mapping (H2F) table update or a GC process; and executing the host write command that requires to process immediately in a batch and then performing the portion of the H2F table update or the GC process when the determination is positive.

Abstract: A memory adaptive temperature controlling method, a storage device, and a control circuit unit are provided. In this exemplary embodiment, the temperature value is obtained according to the temperature measured by the thermal sensor, and the access speed to be reached is calculated according to the temperature change rate within the specific time range and the adjustment percentage when it is determined that the speed-down or speed-up operation is required to be performed. By adjusting the access speed of the memory storage device in a stepwise manner, the temperature of the memory storage device may be stabilized, thereby striking the balance between the temperature stability and the system performance of the memory storage device.

Abstract: A computing system includes a volatile memory, a cache coupled with the volatile memory, and a processing device coupled with the cache and at least one of a storage device or a network port. The processing device is to: generate a plurality of virtual addresses that are sequentially numbered for data that is to be at least one of processed or transferred in response to an input/output (I/O) request; allocate, for the data, a continuous range of physical addresses of the volatile memory; generate a set of hash-based values based on mappings between the plurality of virtual addresses and respective physical addresses of the continuous range of physical addresses; identify a unique cache line of the cache that corresponds to each respective hashed-based value of the set of hash-based values; and cause the data to be directly stored in the unique cache lines of the cache.

Abstract: Systems, apparatuses and methods may provide for technology that programs a plurality of seed values into a plurality of linear feedback shift registers (LFSRs), wherein the plurality of LFSRs correspond to a data word (DWORD) and at least two of the plurality of seed values differ from one another. The technology may also train a link coupled to the plurality of LFSRs, wherein the plurality of seed values cause a parity bit associated with the DWORD to toggle while the link is being trained. In one example, the technology also automatically selects the plurality of seed values based on one or more of an expected traffic pattern on the link (e.g., after training) or a deskew constraint associated with the link.