Abstract: An allocation history is maintained for each node in a multi-node data storage system. The allocation history for each node indicates sets of physical blocks previously allocated to the node to store dirty pages of user data flushed from a cache of the node. The allocation history indicates non-quarantined sets of physical blocks that are currently being used to provide non-volatile data storage to cache flush operations, and quarantined sets of physical blocks not currently being used to provide non-volatile data storage to cache flush operations. Allocation is prevented to any node of any set of physical blocks that is indicated as non-quarantined by any of the allocation histories, and of any set of physical blocks that is indicated as quarantined by any of the allocation histories.

Abstract: Methods and systems for storage services is provided. One method includes configuring by a processor, a database availability group (DAG) storing an active database copy at a first computing node and a passive database copy of the active database copy at a second computing node; initiating a backup operation for backing up the passive database copy from the second computing node; and interfacing with the first computing node by the second computing node for completing the backup operation. The first computing node identifies logs for the backup operation, backs up the identified logs and provides metadata associated with the backup of the identified logs to the second computing node. The second computing node updates metadata for the backup operation such that a backup copy of the passive database copy points to the second node with metadata received from the first computing node.

Abstract: Various embodiments are provided for managing multiport banked memory arrays in a computing system by a processor. One or more conflicts may be eliminated in a multiport banked memory array upon receiving one or more write operations, read operations, or a combination thereof according to a selected priority and access protocol.

Abstract: Provided is an operation method of a controller which controls a memory device. The operation method may include: determining a caching order of plural pieces of map data included in a request map segment including request map data; requesting the request map segment from the memory device; marking data in a marking region which is determined based on the caching order; caching, in the caching order, the plural pieces of map data read from the memory device; and acquiring the request map data from the cached data, depending on whether the data stored in the marking region is changed.

Abstract: A plurality of computing devices are communicatively coupled to each other via a network, and each of the plurality of computing devices is operably coupled to one or more of a plurality of storage devices. Each computing device is operable to access one or more memory blocks within the storage devices and maintain a registry over the same one or more memory blocks. The registry may be adaptively resized according to the access of the one or more memory blocks.

Abstract: A method and a system for data migration on a multi-tiered storage system are provided. The method can include receiving a migration task indicating a dataset to migrate. The method can further include building a plurality of buffers onto at least one high-performance storage tier. The high-performance storage tier can be based on the read speed of that tier. The method can also include referencing a shadow mapping to locate physical data from the dataset stored on a first buffer. The method can include migrating the physical data from the first buffer to a migration destination. The method can further include deallocating the first buffer. The deallocation can allow allocation of additional physical data onto the first buffer for migration.

Abstract: A method for demoting data from a cache comprising heterogeneous memory types is disclosed. The method maintains, for a data element in the cache, a write access count that is incremented each time the data element is updated in the cache. The cache includes a higher performance portion and a lower performance portion. The method removes the data element from the higher performance portion in accordance with a cache demotion algorithm. If the data element also resides in the lower performance portion and the write access count is below a first threshold, the method leaves the data element in the lower performance portion. If the data element also resides in the lower performance portion and the write access count is at or above the first threshold, the method removes the data element from the lower performance portion. A corresponding system and computer program product are also disclosed.

Abstract: A memory device includes a data path having a data bus. The memory device further includes a first one-hot communications interface communicatively coupled to the data bus, and a second one-hot communications interface communicatively coupled to the data bus. The memory device additionally includes at least one memory bank, and an input/output (I/O) interface communicatively coupled to the at least one memory bank via the first one-hot communications interface and the second one-hot communications interface, wherein the first one-hot communications interface is configured to convert a first data pattern received by the I/O interface into one-hot signals transmitted via the data bus to the second one-hot communications interface, and wherein the second one-hot communications interface is configured to convert the one-hot signals into the first data pattern to be stored in the at least one memory bank.

Abstract: Methods, systems, and devices for a memory access gate are described. A memory device may include a controller, memory dice, and a pad for receiving an externally provided control signal, such as a chip enable signal. The memory device may include a switching component for selecting the externally provided control signal or an internally generated control signal. The controller may provide the selected control signal to a memory die. The memory device may determine whether it is operating in a first mode or a second mode, and select the externally provided control signal or the internally generated control signal based on the determination. The first mode may be a diagnostic mode in some cases. The controller may include a secure register whose value may impact or control the switching. An authenticated host device may direct the controller to write the value to the secure register.

Abstract: Techniques for performing cache management includes partitioning entries of a hash table into buckets, wherein each of the buckets includes a portion of the entries of the hash table, configuring a cache, wherein the configuring includes allocating a section of the cache for exclusive use by each bucket, and performing first processing that stores a data block in the cache. The first processing includes determining a hash value for a data block, selecting, in accordance with the hash value, a first bucket of the plurality of buckets, wherein a first section of the cache is used exclusively for storing cached data blocks of the first bucket, storing metadata used in connection with caching the data block in a first entry of the first bucket, and storing the data block in a first cache location of the first section of the cache.

Abstract: A memory system includes a memory controller, a first memory bank having a first I/O bus, a second memory bank having a second I/O bus, and a channel connecting the first I/O bus and the second I/O bus to the memory controller. The channel is used to transmit data between the first memory bank and the memory controller and between the second memory bank and memory controller, and is also used to transmit a command from the memory controller to the first memory bank and the second memory bank. The memory controller includes a bank command scheduler implemented in a hardware logic block. The hardware logic block includes a plurality of direct inputs and is able to determine, based on the plurality of inputs, an order in which to output commands to the first memory bank and the second memory bank over the channel; output a first command to the first memory bank; and output a second command to the second memory bank over the channel.

Abstract: A plurality of memory cells are arranged along a plurality of bit lines and a plurality of word lines. A sense amplifier is connected to each of the bit lines. Arranged along each bit line are at least four memory cells including first to fourth memory cells that are either connected to or disconnected from one of the bit lines by means of first to fourth switching elements according to an active or inactive state of first to fourth word lines. The first memory cell stores a first bit value, the second memory cell stores a second bit value, and the third and fourth memory cells each store a third bit value. A memory cell array control circuit activates and then deactivates the third and fourth word lines, subsequently activates the first and second word lines, and then activates the sense amplifier.

Abstract: A memory device having a memory array with a plurality of memory addresses and a controller operably coupled to the memory array is described. The controller is configured to store a sketch comprising d rows and w columns, wherein d and w are positive integers. Each of the d rows corresponds to a different one of d hash functions. The controller is also configured to detect an event associated with a first memory address of the plurality of memory addresses and to hash the first memory address with each of the d hash functions to generate a corresponding d sketch locations. The controller is further configured to adjust, for each of the d sketch locations, a stored sketch value by a first amount corresponding to the event.

Abstract: A memory device having a memory array and a controller operably coupled to the memory array is described. The controller is configured to store a sketch comprising d rows and w columns, wherein d and w are positive integers. Each row corresponds to a different one of d hash functions. The controller is also configured to detect an event associated with a memory address and to hash the memory address with each of the d hash functions to generate a corresponding d sketch locations. The controller is further configured, for each of the d sketch locations, to set a detection window flag, if it is not already set, and to adjust a stored sketch value by an amount corresponding to the event. The controller is also configured to evaluate a summary metric corresponding to the stored sketch value in each of the d sketch locations to determine if a threshold value has been reached.

Abstract: A storage volume functioning at least in part as cache for a tiered storage system, the storage volume having an in-memory write extent consisting of write-accessed grains retrieved from a plurality of hot extents in a first tier of the tiered storage system, where the in-memory write extent is a same size as a block erase size of a solid-state drive tier of the tiered storage system. The storage volume further having an in-memory read extent consisting of read-accessed grains retrieved from the plurality of hot extents in the first tier of the tiered storage system.

Abstract: A computer-implemented method, according to one embodiment, includes: receiving an unmap command, the unmap command identifying a first logical extent located in a higher storage tier of a multi-tiered data storage system having the higher storage tier and a lower storage tier, sending an instruction to unmap the first logical extent from the higher storage tier, sending an instruction to decrement a heat associated with the unmapped first logical extent in response to sending the instruction to unmap the first logical extent, sending an instruction to remove the unmapped first logical extent from the higher storage tier, selecting, using a heat map, at least one second logical extent located in the lower storage tier for promotion to the higher storage tier, and sending an instruction to relocate the at least one second logical extent from the lower storage tier to the higher storage tier.

Abstract: A storage cluster is provided. The storage cluster includes a plurality of storage nodes coupled together as the storage cluster. The plurality of storage nodes is configured to assign data to two or more logical arrays and the plurality of storage nodes is configured to establish data striping across the plurality of storage nodes for user data of each of the two or more logical arrays.

Abstract: A computer-implemented method can include obtaining tape data for one or more tapes. The tape data can include pointer data corresponding to a first file. The method can further include determining, based on the tape data, that the first file is stored on a first tape of the one or more tapes. The first tape can have an export status. The method can further include determining that the pointer data includes a pointer to the first tape and a pointer to a second tape. The second tape can have a non-export status. The method can further include storing at least a portion of the tape data. The method can further include initiating, based on the first tape having the export status, a deactivation of the pointer to the first tape.

Abstract: A data storage device includes a nonvolatile memory device; and a controller suitable for setting a termination condition of a garbage collection operation based on an over-provisioning ratio of the nonvolatile memory device, performing the garbage collection operation, and terminating the garbage collection operation according to the termination condition.

Abstract: In a method of operating a storage device, the storage device includes a plurality of memory blocks. A data write request and target data to be written are received. Using a data classifier, such as a neural network model, the target data is assigned to a stream selected from a plurality of streams based on a data property of the target data. The target data is written into a memory block assigned to a stream selected for assignment of the target data, such that target data that has been assigned to a stream are written into the one or more memory blocks assigned to the stream.