Patents Examined by Charlie C Stevenson
  • Patent number: 6583870
    Abstract: A provisional inspection recipe is prepared using a simulated defective wafer having a simulated defect layer which has the variations in height and plane shape with respect to a simulated normal layer. An actual defect inspection for the simulated defective wafer is carried out by means of a defect inspection system to compare a detected defect data with a previously obtained simulated defect data of the simulated defective wafer to quantify a defect detection sensitivity. The provisional inspection recipe is modified while changing tentative recipe parameters until a desired defect detection ratio is obtained. When the desired defect detection ratio is obtained, the tentative recipe parameters at the time are decided as recipe parameters adaptive for the defect inspection system.
    Type: Grant
    Filed: May 29, 2001
    Date of Patent: June 24, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tomonobu Noda