Abstract: A system and method enable a designer to design an application using a design tool, deploy the application for execution, and subsequently view statistics related to the execution within the design tool. The designer uses the design tool to create an application flow for the application, and the design tool then generates software code for such application. In generating software code, the design tool inserts markers in the application code that demarks the boundaries between nodes in the application flow. When the application is executed, a log is created in accordance with the markers such that data is logged for nodes traversed during the execution of the application. Using the logged data, statistics are calculated for one or more of the nodes. These statistics are provided to the design tool and, in the preferred embodiment, displayed in conjunction with the application flow in the user interface of the design tool.

Abstract: In one embodiment, a method for sharing data displayed on a user's computer screen includes displaying a movable tile on the user's computer screen, the tile being positionable on the computer screen to identify data displayed on the user's computer screen and selected for sharing with one or more remote users. The method further includes transmitting the data identified by a position of the tile on the user's computer screen to the remote users, receiving shared data from one of the remote users, and displaying the shared data on the user's computer screen. The identified data includes only a portion of data displayed on the user's computer screen and the shared data corresponds to data displayed on a portion of said remote user's computer screen.

Abstract: Some embodiments of the invention provide novel methods for editing the value of an attribute of a media item (e.g., a media content or a media operation) for a media editing application. Such attributes of a media item can include scale, rotation, opacity, pan, volume, etc. In some embodiments, a media editing application represents the changing value of such an attribute over a duration (e.g., a duration of time, a duration of frequencies, etc.) as a key-indexed geometry. A user of the media editing application can manipulate these geometries to change the attribute value over a duration. Such geometries may include graphs and shapes. For such applications, some embodiments provide novel compressed geometric representations (i.e., collapsed views) of one or more uncompressed key-indexed geometries (e.g., graphs or shapes).

Abstract: A system and method are provided for executing an executable clinical practice guideline for providing guidance in treating a patient. A guideline repository stores a plurality of executable clinical practice guidelines. At least one interface receives clinical context data associated with at least one of the patient and the patient's treatment. A system server, upon receipt of said clinical context data, automatically chooses an appropriate guideline and controls a display to display the guideline at its present level of abstraction, and a visual navigator which defines the current level of abstraction. The level of abstraction is changed via a user input between a higher level of abstraction in which fewer more abstract steps of the guidelines are displayed and a lower level of abstraction in which more, detailed steps are displayed.

Abstract: A method and system for intelligent electronic information processing. The method and system include selecting one or more portions of a set of electronic information including any unwanted portions that have been reviewed and are to be eliminated from display. The selected portions are recording thereby eliminating any unwanted previously reviewed portions of the set of electronic information from display with any additional sets of electronic information. The method and system may be used to review search engine results, electronic auction results, syndicated news items and to purchase tickets for transportation and events and for reserving lodging.

Abstract: A signal processing device includes a converting unit, a filtering unit, a differential computing unit, and a phase difference computing unit. The converting unit samples two alternating signals with a predetermined period and converts the sampled level values into digital alternating signal data. The filtering unit filters the two digital alternating signal data generated by the converting unit so as to abstract digital alternating signal data having a predetermined frequency, and the filtering unit comprises an adaptive digital filter. The differential computing unit computes differentials of the digital alternating signal data generated by the filtering unit. The phase difference computing unit computes phase difference using the two digital alternating signal data generated by the filtering unit, and the two digital alternating signal data generated by the differential computing unit.

Abstract: A minimal area integrated polyphase interpolation filter uses a symmetry of coefficients for a channel of input data. The filter includes an input interface block for synchronizing the input signal to a first internal clock signal; a memory block for providing multiple delayed output signals; a multiplexer input interface block for outputting a selected plurality of signals for generating mirror image coefficient sets in response to a second set of internal control signals, a coefficient block for generating mirror image and/or symmetric coefficient sets, and to output a plurality of filtered signals, an output multiplexer block for performing selection, gain control and data width control on said plurality of filtered signals, an output register block synchronizing the filtered signals, and a control block generating clock signals for realization of the filter and to delay between two channels to access a coefficient set, thereby minimizing hardware in the filter.

Abstract: A Montgomery multiplier for providing security of information used in smart cards from hacking by a differential power analysis attack by minimizing power consumption difference by the input data. More particularly, the Montgomery multiplier applies an asynchronous dual rail lines method wherein two lines DATAFALSE and DATATRUE are used to represent one binary data such that in order to represent binary data ‘0’, a logical high signal is applied to the DATAFALSE line, and a logical low signal is applied to the DATATRUE line. Conversely, to represent binary data ‘1’, a logical low signal is applied to the DATAFALSE line, and a logical high signal is applied to the DATATRUE line. That is, when the data is represented by the asynchronous dual rail lines method, whatever the binary data value is, the same number of logical high states and logical low states are generated. As a result, whatever binary data is to be operated, the power consumption difference of the circuit is minimized.

Abstract: A divide-by-N clock frequency divider producing N non-overlapping clocks each with precise 1/N duty ratio is implemented by a counter, a token generator and N-bit shift register. Every N clock cycles, a pulse is generated as a token from a logical combination of signals from the counter. The pulse is passed along a shift register having balanced load capacitances under control of the clock edge, ensuring a precise 1/N duty ratio that is unaffected by load capacitances from the fault state detection and/or reset circuitry. In this manner, a higher operating frequency may be achieved with low power consumption.

Abstract: A data processor computes an absolute difference between portions of first and second data elements. At least a part of the first and second data elements are compared to determine which data element is larger. A first comparison result value is produced if the first element is larger and a second comparison result value if the second element is larger. An absolute difference is computed between a portion of the first and second data elements. One of the portions is inverted and added to the other portion and to the comparison result to produce an intermediate result. An absolute difference is provided with improved speed either as the intermediate result or an inverted version of the intermediate result dependent on the comparison result.

Abstract: A conditional select adder having a carry generating unit which generates a carry of two n-bit input data units X0-Xn-1, and Y0-Yn-1, and a sum generating unit which generates the sum of the input data, is provided. The carry generating unit comprises a first input unit which receives predetermined data based on the input data Xi and Yi; a second input unit which receives the initial carry; and a selection unit which receives the result of performing an XOR operation on the input data Xi and Yi, in which according to the XOR result, either predetermined data based on the input data Xi and Yi input to the first input unit, or the initial carry input to the second input unit is selected and output as a carry. The sum generating unit calculates a sum using the carry generated by the carry generating unit. Advantages include reducing power consumption, chip area, logic count, and delay time.

Abstract: A pseudo-random number generator comprises a linear feedback register for generating pseudo-random numbers; and a signal generator for generating a shift clock for operating a linear feedback register and predetermined input data. The linear feedback register has a plurality of registers connected in series, a first logical operation circuit for taking logical operation of output data from predetermined registers to deliver the result thereof, and a second logical operation circuit for taking logical operation of input data supplied from the outside and output data of the first logical operation circuit to supply the result thereof to any one of the registers.

Abstract: A method for designing Wavelets for communications and radar which combines requirements for Wavelets and finite impulse response FIR filters including no excess bandwidth, linear performance metrics for passband, stopband, quadrature mirror filter QMF properties, intersymbol interference, and adjacent channel interference, polystatic filter design requirements, and non-linear metrics for bandwidth efficient modulation BEM and synthetic aperture radar SAR. Demonstrated linear design methodology finds the best design coordinates to minimize the weighted sum of the contributing least-squares LS error metrics for the respective performance requirements. Design coordinates are mapped into the optimum FIR symbol time response.

Abstract: A device for performing numerical value conversion of a digital input value in a first unit to a second unit being a natural unit includes a look-up table storing an array of coefficients for performing the numerical value conversion. The look-up table is indexed using a first parameter to provide a selected coefficient. An arithmetic logic unit (ALU) is coupled to receive the digital input value and the selected coefficient and perform the numerical value conversion based on a first equation using the selected coefficient to compute a digital output value in the second unit. The first unit can be an arbitrary ADC unit and the second unit is a natural unit of physical measurement, such as volts, amperes, degree Centigrade. Furthermore, the device can be used to perform numerical value conversion from the arbitrary unit to the natural unit having a linear or a non-linear relationship.

Abstract: There is disclosed method, software and apparatus for evaluating a function f in a computing device using a reduction, core approximation and final reconstruction stage. According to one embodiment of the invention, an argument reduction stage uses an approximate reciprocal table in the computing device. According to another embodiment, an approximate reciprocal instruction I is operative on the computing device to use the approximate reciprocal table such that the argument reduction stage provides that—C:=I(X) and R:=X×C?1, the core approximation stage provides that p(R) is computed so that it approximates f(1+R), and the final reconstruction stage provides that T=f(1/C) is fetched and calculated if necessary, and f(X) is reconstructed based on f(X)=f([1/C]×[X×C])=g(f(1/C), f(1+R)).

Abstract: A modular arithmetic apparatus has a plurality of base parameter sets in read only memories. A base selection unit in the modular arithmetic apparatus selects one of the base parameters sets according to an input modulus p. A plurality of operation units 30, in the modular arithmetic apparatus, perform an arithmetic operation according to the selected base parameter set in parallel and obtain an arithmetic result.

Abstract: Operation of an adaptive filter includes determining a first filter coefficient and determining a second filter coefficient based on the first filter coefficient, in one embodiment, and in another embodiment includes comparing pseudo-error counts generated for each of several time intervals and setting filter coefficients based on the comparison. Adaptive filter coefficient generating apparatus includes a pseudo-error count generator adapted to receive the output of the adaptive filter and to generate counts of pseudo-errors occurring during successive time intervals, and a filter coefficient generator generating filter coefficients for the adaptive filter in response to the pseudo-error counts.

Abstract: An integrated circuit device (100) includes circuitry for providing a first shift argument (L[4:0]) indicating shift positions in a first direction and circuitry for providing a second shift argument (R[4:0]) indicating shift positions in a second direction. One rotate stage (ROTATE STAGE 1), in a plurality of rotate stages, is coupled to receive the initial data argument. Each rotate stage, other than the one rotate stage, is coupled to receive a data argument from an output of another one of the rotate stages. Further, each rotate stage is operable to rotate the data argument input into the corresponding rotate stage in response to less than all bits of at least one of the first and second shift arguments. At least one rotate stage is operable to rotate the data argument input into the corresponding rotate stage in response to a sum of respective bit positions of the first and second shift arguments.

Abstract: In this invention, a random number generation apparatus inputs unperiodic random noise n generated by a noise source 1 to a waveform shaping circuit 2 to generate a random pulse wave P1. Next, the random number generation apparatus inputs the random pulse wave P1 and a clock c1 from an oscillator 3 to a sample-and-hold circuit 4 to generate a constant periodic binary pulse sequence P2. Subsequently, the binary pulse sequence P2 and a half divided clock c2, which is the clock c1 half divided by the divider 5, are inputted to a switching circuit 6, and the polarity of the binary pulse sequence P2 is reversed at intervals of one period to output a smoothed binary pulse sequence P3 in which appearance balance of 1/0 code is smoothed.

Abstract: An interface receiver, which is part of an interface that allows the transfer of data between two incompatible I/O standards, includes a crossbar and a barrel shifter that can be implemented using multiplier-accumulator blocks. The crossbar reorders an incoming burst of data and writes the data into a larger data column where the data is barrel-shifted using multiplier-accumulator blocks and transferred out of the receiver when an end-of-packet is detected or the shifted data column as seen from outside the interface receiver is full.