Abstract: A storage device may include a memory and a controller. The controller may input, to the memory, a read command for a first plane among the plurality of planes through a first path connected to the first terminal, receive, from the memory, read data for the read command through a second path connected to the second terminal, and input, to the memory, one or more additional commands through the first path in parallel with an operation of receiving the read data during an expected output time of the read data.

Abstract: Novel tools and techniques are provided for implementing migration of one or more drives, and more particularly to methods, systems, and apparatuses for implementing migration of one or more drives by setting one or more indications on a memory of the one or more drives. A controller for a redundant array of independent disks can be configured to set a first indication indicating a first drive is safe to migrate or not safe to migrate and store the first indication in a first memory on the first drive. The first drive can be a mirror of a second drive. The controller can further be configured to set a second indication indicating the second drive was offline or not offline and store the second indication in the first memory on the first drive.

Abstract: A storage device may write data to a memory as requested by an external device. Subsequently, the storage device may update an attribute of the data based on an increment of an average program-erase cycle of the memory and whether the data has been overwritten. The attribute of the data may be one of a plurality of candidate attributes and the plurality of candidate attributes may include hot, cold, and warm.

Abstract: Methods and apparatus to implement an integrated circuit including both dynamic random-access memory (DRAM) and static random-access memory (SRAM). In one embodiment, the integrated circuit comprises a static random-access memory (SRAM) device to store a first portion of data of a processor, a dynamic random-access memory (DRAM) device to store a second portion of the data of the processor, and a memory control circuit to read from both the SRAM and DRAM devices, a first set of bits of a first word to be read from the SRAM device and a second set of bits of the first word to be read from the DRAM device.

Abstract: A storage device may group a plurality of zone clusters, each cluster including at least one zone. The storage device may then store target data in a target zone cluster. For example, the storage device may determine a target zone for storing target data, using the sum of a write count and a seed value for the target zone cluster.

Abstract: Aspects of the disclosure relate to a dynamic caching platform. The dynamic caching platform may train a machine learning model based on historical complexity score information. The dynamic caching platform may receive information streams from a client metaverse device and a metaverse host system. The dynamic caching platform may generate a complexity score based on the interaction information streams using the machine learning model. The dynamic caching platform may compare the complexity score to complexity thresholds. Based on the comparison, the dynamic caching platform may identify caching rules. The dynamic caching platform may cache interaction information based on the caching rules. The dynamic caching platform may update the complexity score using the machine learning model. The dynamic caching platform may update the caching rules based on the updated complexity score. The dynamic caching platform may cache interaction information based on the updated caching rules.

Abstract: Techniques for parallel processing using hazard detection and mitigation are disclosed. An array of compute elements is accessed. Each compute element within the array of compute elements is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements. Control for the compute elements is provided on a cycle-by-cycle basis. Control is enabled by a stream of wide control words generated by the compiler. Memory access operations are tagged with precedence information. The tagging is contained in the control words. The tagging is provided by the compiler at compile time. Memory access operations are monitored. The monitoring is based on the precedence information and a number of architectural cycles of the cycle-by-cycle basis. The tagging is augmented at run time, based on the monitoring. Memory access data is held before promotion, based on the monitoring.

Abstract: A storage device includes a memory apparatus configured to store logical to physical (L2P) information, and a controller coupled to be in communications with the memory apparatus and configured to selectively change a map update mode based on a map update history after performing a map management operation on the L2P information.

Abstract: A decryption engine can decrypt encrypted data read from a physical address in a memory of a data storage device. To decrypt the data, the decryption engine can use a tweak value that is generated from a logical address associated with the physical address. To reduce latency, the tweak value can be generated in parallel with the translation of the logical address to the physical address. The tweak value can be stored in a tweak buffer in the decryption engine until needed and can be indexed by a tag associated with a process in a host that is requesting the data. The tweak buffer can use static random-access memory (SRAM) or a content-addressable memory (CAM), for example. Other embodiments are provided.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for controlling, by an on-chip memory controller, a plurality of hardware components that are configured to perform computations to access a shared memory. One of the on-chip memory controller includes at least one backside arbitration controller communicatively coupled with a memory bank group and a first hardware component, wherein the at least one backside arbitration controller is configured to perform bus arbitrations to determine whether the first hardware component can access the memory bank group using a first memory access protocol; and a frontside arbitration controller communicatively coupled with the memory bank group and a second hardware component, wherein the frontside arbitration controller is configured to perform bus arbitrations to determine whether the second hardware component can access the memory bank group using a second memory access protocol different from the first memory access protocol.