Abstract: Scheduling memory accesses in a memory system having a multiple ranks of memory, at most r ranks of which may be powered up concurrently, in which r is less than the number of ranks. If fewer than r ranks are powered up, a subset of requested powered down ranks is powered up, such that at r ranks are powered up, the subset of requested powered down ranks to be powered up including the most frequently accessed requested powered down ranks. Then, if fewer than r ranks are powered up, a subset of unrequested powered down ranks is powered up, such that a total of at most r ranks is powered up concurrently, the subset of unrequested powered down ranks to be powered up including the most frequently accessed unrequested powered down ranks.

Abstract: In programmable equipment where it is either undesirable or impractical to construct the program code with embedded licensing decision points, the program is constructed by hard-coding the license rights into the program code at program build time. License permissions are obtained from a sales order system and used to produce a code image, or select a pre-existing, pre-validated code image which contains only those features, facilities, or capabilities allowed by the applicable license rights for that particular sales order and on that particular programmable unit. Functionality of the device is updated as appropriate by use of a bootloader on the device for installation of a firmware image. In this way, the invention overcomes the technical limitations inherent in such devices by reprogramming the device to alter device functionality in keeping with rights and privileges added or deleted therefrom with regard to software installed thereon.

Abstract: An information handling system (IHS) includes temperature-compensated power control by a voltage regulation (VR) module to: (i) receive a monitored current (Imon) value from a current sensor integrated into the VR module; (ii) receive a temperature value from the temperature sensor also integrated into the VR module; (iii) determine a temperature-compensated Imon value based at least in part on the Imon value, the temperature value, and an empirically-derived temperature coefficient defined at the Imon value and the temperature value; and (iv) control the voltage-regulated power at least in part based on the temperature-compensated Imon value. The empirically-derived temperature coefficient adjusts for nonlinear portions of temperature coupling relationship between a portion of an integrated circuit (IC) die that can include the current sensor and the temperature sensor and a temperature experienced by by active portion of VR module.

Abstract: A system with a local data collector that collects power management data for a subsystem. The local data collector can determine whether a first formatting associated with a first channel between the local data collector and a system power management data collector is equivalent to a second formatting associated with a second channel between the local data collector and the system power management data collector, and in response to a determination that the first formatting and second formatting are not equivalent format the power management data according to the first formatting; store the power management data formatted according to the first formatting in a first location in a memory; format the power management data according to the second formatting; and store the power management data formatted according to the second formatting in a second location the memory.

Abstract: A power-supply control apparatus includes a processor that executes a process. The process includes calculating, for a first time period, a first predictive value of total power consumption by the power-supply control apparatus and one or more other power-supply control apparatuses to which power is supplied from a power supply; and determining whether to allow a storage battery to be charged in the first time period based on the first predictive value for the first time period and previous information that is related to the first predictive value and obtained in a second time period before the first time period.

Abstract: A computer-implemented method dynamically limits peak power consumption in processing nodes of an IHS. A power management micro-controller receives processing node-level power-usage and workload data from several node controllers, including current power consumption and a current workload, for each processing node within the IHS. A total available system power of the IHS is identified including a peak power output capacity and a sustained output power capacity. At least one node peak power threshold is determined based on the power-usage and workload data for each of the processing nodes. The node controllers are triggered to determine and set a device peak power limit for each of several variable performance devices within each of the processing nodes based on the node peak power threshold, wherein each of the variable performance devices dynamically adjusts a value of a corresponding device performance metric based on the device peak power limit.

Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

Abstract: A system synchronizes a PC exhibiting latency of operations to a biosensor enabled microcontroller with real-time clock by providing an encoding scheme that captures the subject's absolute reaction time transmits the subject's reaction time from the PC exhibiting latency to the microcontroller with real-time clock. The system includes a transmitter that transmits a stimulus signal from the PC exhibiting latency, an input device indicating the subject's response to the stimulus signal, an encoding circuit adapted to encode a difference in time between the stimulus signal and the subject's response to the stimulus signal, an emitter adapted to transmit the encoded difference signal representing the subject's reaction time, and a complementary receiver adapted to detect the encoded difference signal.

Abstract: Bandwidth for information transfers between devices is dynamically changed to accommodate transitions between power modes employed in a system. The bandwidth is changed by selectively enabling and disabling individual control links and data links that carry the information. During a highest bandwidth mode for the system, all of the data and control links are enabled to provide maximum information throughout. During one or more lower bandwidth modes for the system, at least one data link and/or at least one control link is disabled to reduce the power consumption of the devices. At least one data link and at least one control link remain enabled during each low bandwidth mode. For these links, the same signaling rate is used for both bandwidth modes to reduce latency that would otherwise be caused by changing signaling rates. Also, calibration information is generated for disabled links so that these links may be quickly brought back into service.

Abstract: Technologies are generally described for selectively charging a capacitor coupled to a memory. Example electronic devices described herein may include a memory; a capacitor coupled to the memory; a power supply configured to supply power at least to the capacitor; a switch coupled between the power supply and the capacitor; and a switch controller coupled to the switch and configured to: determine whether the electronic device is in a safety mode or in a normal mode, and control an operation of the switch, based on the determination. So, the supply of the power from the power supply to the capacitor is selectively controlled.

Abstract: A voltage regulator power reporting offset system includes a monitored power reporting subsystem that determines a monitored power level, offsets the monitored power level using voltage regulator operation offset information to provide a first offset monitored power level, and reports the first offset monitored power level to voltage regulator operation components. A processor power reporting component receives the report of the first offset monitored power level from the monitored power reporting subsystem. A processor power reporting offset subsystem receives the report of the first offset monitored power level from the processor power reporting component, offsets the first offset monitored power level using the processor operation offset information to provide a second offset monitored power level that is different than the first offset monitored power level, and reports the second offset monitored power level to a processing system.

Abstract: Successful communication required between external devices is achieved. A content data processing unit is connected to an external device through a first line. A communication unit is connected to the external device through a second line. The content data processing unit represents, for example, a content data transmitting unit that transmits content data to the external device, or a content data receiving unit that receives the content data from the external device. The communication unit transmits an inquiry signal to the external device through the second line in a state in which the first line is unavailable. For example, in a case where the interface unit is in a standby state, it is possible to inquire a required item to the external device while the state is maintained. Since it is possible to decrease power consumption of the external device as much as possible, it is possible to contribute to saving of energy of the external device.

Abstract: A fault processing subsystem of an electronics assembly, senses an alarm state at an output of a first power distribution element of multiple power distribution elements arranged in a hierarchy in the electronics assembly. The first element is at a level of the hierarchy other than the top level, and the alarm state corresponds to an output of the first element being different than an expected output of that element. The fault processing subsystem commands, in response to the sensing the alarm state, the first element to disable via a control input to the first element. In response to the fault processing subsystem thereafter sensing an alarm state at the power output of the commanded element, the fault processing subsystem commands an element at the next higher level in the hierarchy from the first element to disable.

Abstract: An electronic device is provided that includes a base, a processor, and a tablet having a front surface, a rear surface and a bottom edge surface. A processor may operate at a first operating condition when the tablet is coupled to the base, and the processor may operate at a second operating condition when the tablet is not coupled to the base. The tablet may include a heat conducting device and an active edge. The heat conducting device may conduct heat from the processor to the active edge where the heat may be dissipated using supplemental cooling.