Patents Examined by Cheryl Figlin
  • Patent number: 5233135
    Abstract: A technique for forming metal interconnect signal lines provides for planarization of an interlevel dielectric layer. A thin layer of material which can function as an etch stop, such as a metal oxide, is formed over the interlevel dielectric. An alignment process is used to pattern and define openings through the etch stop layer where contacts to underlying conductive regions will be formed. Another insulating layer is formed over the etch stop layer, and patterned to define all interconnect signal lines. When the signal line locations are etched away, the etching process stops on the etch stop layer in regions where the signal lines will be, and continues through to the underlying conductive layer where contacts are needed. A metal refill process can be used to then form interconnects and contacts within the etched holes, followed by an anisotropic etchback to remove any metal which lies on top of the upper insulating layer.
    Type: Grant
    Filed: June 28, 1991
    Date of Patent: August 3, 1993
    Assignee: SGS-Thomson Microelectronics, Inc.
    Inventors: Fusen E. Chen, Frank R. Bryant, Girish A. Dixit