Abstract: A backside illuminated CCD imaging sensor for reading out image charges from wells of the array of pixels is significantly improved for blue, UV, far UV and low energy x-ray wavelengths (1-5000.ANG.) by so overthinning the backside as to place the depletion edge at the surface and depositing a thin transparent metal film of about 10.ANG. on a native-quality oxide film of less than about 30.ANG. grown on the thinned backside. The metal is selected to have a higher work function than that of the semiconductor to so bend the energy bands (at the interface of the semiconductor material and the oxide film) as to eliminate wells that would otherwise trap minority carriers. A bias voltage may be applied to extend the frontside depletion edge to the interface of the semiconductor material with the oxide film in the event there is not sufficient thinning.

Abstract: In order to fabricate gates for an integrated circuit formed on a semiconductor substrate of silicon covered with at least one layer of oxide, one layer of polycrystalline silicon and if necessary one layer of silicide, an initial step consists in successive deposition of a silicon nitride layer and a silicon oxide layer, openings in these two layers being then formed by photoetching in a second step. In a third step, the silicon oxide layer is partly removed by deoxidation in order to bare the nitride layer over a certain distance which determines the spacing between two consecutive gates, oxide being then grown within the openings formed during the second step. The final step consists in removing the nitride regions uncovered during the third step as well as the subjacent silicide layer if this latter is provided and the subjacent polycrystalline silicon layer.

Abstract: A semiconductor laser device is fabricated by forming a first semiconductor layer of N type GaAs to be a current narrowing layer on a P type GaAs semiconductor substrate, forming a second semiconductor layer of P type AlGaAs on the first semiconductor layer, removing said second semiconductor layer by etching except the proximity of the portion to be the end surface of a resonator, forming a striped groove which is deep enough to penetrate the first semiconductor layer and extends to that direction which crosses the surface to be the end surface of the resonator and, depositing a lower clad layer, an active layer, an upper layer and a contact layer in this order.

Abstract: In the fabrication of bipolar transistors by the single poly process, polysilicon sidewalls are formed along portions of a polysilicon layer that functions as a device contact. The sidewalls serve both as dopant sources which determine the width of underlying base and emitter regions, and as contacts to those devices. Since the thickness of the polysilicon sidewalls, and hence the width of the underlying device regions, are precisely controllable through conventional polysilicon deposition techniques, relatively relaxed design rules can be employed while making possible the formation of emitters having widths less than one-half of a micron.

Abstract: An avalanche photodetector of the heterojunction type comprises an intermediate region between two end regions made from distinct semiconductor materials. The intermediate region comprises a lattice of slices of varying thicknesses of alternating layers of the material of the end regions thus forming a system of coupled quantum wells whose thicknesses and whose number of slices are determined so that the response time of the photodetector is less than a maximum given time, while maintaining the number of coupled quantum wells to a minimum.

Abstract: A structure for isolating a bipolar transistor (100) from an adjacent transistor includes a first silicon dioxide isolation region (110) laterally surrounding the transistor and a conductive channel stop region (112) laterally surrounding the silicon dioxide isolation region. The channel stop region allows electrical potential of the substrate (102) to be controlled and the silicon dioxide isolation region prevents the channel stop from contacting the transistor.

Abstract: This absorbant is of the type formed by superlattice constituted by a stack of films of two different semiconductor materials having gaps of different heights. Thus, a potential well is produced in each film corresponding to the semiconductor with the smallest gap and a potential barrier in each film corresponding to the semiconductor with the largest gap. This saturatable absorbant is characterized in that the films corresponding to the semiconductor with the smallest gap have a thickness, which can assume two values, one small and the other large.Application in optics to the production of mode locking lasers and all optical logic gates.

Abstract: A process is disclosed for fabricating complementary insulated gate field effect transistors including doped field isolation regions and optional punch through protection. In one embodiment of invention, a silicon substrate is provided which has N-type and P-type surface regions. First and second masks are formed overlying active areas of the two surface regions. A third mask is then formed overlying the first region and the first mask. P-type impurities are implanted into the second region with an implant energy which is sufficient to penetrate through the second mask but insufficient to penetrate through the third mask. A second P-type implant is performed with an implant energy insufficient to penetrate through either mask. The first implant will aid in preventing punch through while the second implant dopes the field region. A fourth mask is then formed overlying the second region and the second mask.

Abstract: A method of forming CMOS transistors with self-aligned field regions. First and second spaced apart areas are provided on a silicon substrate. A masking member is formed protecting the first of said areas and exposing the second. The exposed area is doped with a p-type material which is driven in to form a p-well. The same region is again doped with additional p-type material after which the CMOS transistors are fabricated.

Abstract: An infrared photodetector is formed of a heavily doped p-type Ge.sub.x Si.sub.1-x /Si superlattice in which x is pre-established during manufacture in the range 0 to 100 percent. A custom tailored photodetector that can differentiate among close wavelengths in the range of 2.7 to 50 microns is fabricated by appropriate selection of the alloy constituency value, x, to establish a specific wavelength at which photodetection cut-off will occur.

Abstract: An n-type buried layer is selectively formed in a surface region of a p-type semiconductor substrate. At least one insulating film is formed on the semiconductor substrate. A first opening is formed on the buried layer in the insulating film. An n-type polycrystalline silicon layer is formed in the first opening connected to the buried layer. A second opening is formed on the buried layer of the insulating film. An n-type monocrystalline silicon layer is formed in the second opening connected to the buried layer. A p-type base region is formed in the monocrystalline silicon layer and a collector region is formed in the remaining portion of the monocrystalline silicon layer. An emitter region is selectively formed in the base region.

Abstract: A process of providing semi-insulating thin film resistors with closer tolerance values by furnance-annealing the film to increase is resistance to less than the final intended value, and then focused heat source-annealing the film to within a close tolerance of the final intended value.

Abstract: A buried-heterostructure distributed feedback laser is described, including a grating structure at a surface of a nonplanar cladding layer. The grating structure can be made by transfer of a pattern by ion milling, the pattern being defined in an ion-beam resist layer, e.g., by direct-writing electron-beam exposure. Low-threshold, high-power lasers are obtained with a commercially favorable yield.

Abstract: MOS process for forming field-effect devices in self-alignment with a buried oxide region. Oxygen is implanted in alignment with masking members after gates have been defined from the masking members. The masking members block the oxygen implantation and thus the channel regions of subsequently formed transistors are self-aligned with openings in the buried oxide layer.

Abstract: A method is set forth of manufacturing a three-layer electrode system, more particularly for use in CCD image sensors. A group of first electrodes (4A,B,C) is formed on a gate oxide layer (3) by a first silicon layer (4). After etching away the exposed gate oxide, a first thermal oxidation is carried out. Subsequently, an anti-oxidation layer (6) of, for example, silicon nitride is provided, on which a second silicon layer (7) is provided, from which a group of second electrodes (7A,B) is formed. The second electrode overlap the first electrodes in part, whereupon they are subjected to a second thermal oxidation. The exposed part of the anti-oxidation layer (6) is removed by anisotropic plasma etching which maintains parts (6A) on the edge of the first electrodes and under projecting oxide edges. After a third thermal oxidation, a third silicon layer (9) is provided, from which a third group of electrodes (9A,B) is formed, which partially overlap first and second electrodes.

Abstract: A method of fabrication of a control transistor for a flat-panel display screen involves the following steps:deposition of conductive material such as ITO on a substrate;etching of electrodes in the conductive material;successive depositions of layers formed of metallic material followed by n-doped amorphous semiconductor material;etching of a column and a connecting element in contact with the electrode;successive depositions of layers formed of undoped amorphous semiconductor material followed by insulating material and then by metallic material;etching in the three layers which have just been deposited of a row which overlaps the column and the connecting element.

Abstract: An image sensor device comprising a semiconductor substrate having a number of surface-adjoining channel regions. The channel regions are separated from each other by surface-adjoining channel separation zones. The channel regions further adjoin an underlying semiconductor zone extending substantially parallel to the surface. The channel regions have doping concentrations which exceed that of the semiconductor zone. The semiconductor zone has a dopant concentration which exceeds the dopant concentration of the semiconductor substrate. The semiconductor zone has a varying thickness which has minima at the areas of the centers of the channel regions. In such an image sensor device, a potential distribution can be obtained which strongly suppresses blooming realized at right angles to the surface that the occurrence of blooming is strongly suppressed. The invention also relates to a method of manufacturing this image sensor device.

Abstract: The invention relates to a method for the manufacture of thin film field effect transistors of the type having self-alignment of the electrodes and obtained on an insulating substrate.The method comprises two constructional variants making it possible to produce a submicron gate electrode determining a minimum channel length.The invention is applicable to the field of large surface or area microelectronics and in particular to the control and addressing of a flat liquid crystal screen or an image sensor.

Abstract: Ultra low-power GaAs complementary junction field effect transistors are implemented in the design of complementary integrated circuits using a planar technology in conjunction with multiple and selective ion implantation. Both junction FETs, namely the p and n channel devices, are enhancement mode devices and biased in the forward direction thus leading to the advantageous DCFL (directly coupled field effect transistor logic) with one power supply, low power dissipation and high packing densities, all prerequisites for VLSI (very large scale integration).

Abstract: A self aligned, nonoverlapping gate structure for a charge coupled device is fabricated by depositing three sets of interleaved polysilicon gate electrodes. The first set of electrodes is applied in a planar form and sized to a width of about one-third the spacing of the electrodes of the first set. The second and third sets of electrodes are applied to overlap, in turn, portions of the previously applied electrodes. A thick shield layer of SiO.sub.2 is deposited and patterned atop the first and second sets of gate electrodes. After deposition of the third set of electrodes, the shield layers are removed to provide passageways extending beneath the overlapping portions of the second and third sets of electrodes. Such overlapping portions are then removed by etching through the passageways, to produce a nonoverlapping, generally planar gate structure.