Abstract: A cache system, having cache sets, a connection to a line identifying an execution type, a connection to a line identifying a status of speculative execution, and a logic circuit that can: allocate a first subset of cache sets when the execution type is a first type indicating non-speculative execution, allocate a second subset when the execution type changes from the first type to a second type indicating speculative execution, and reserve a cache set when the execution type is the second type. When the execution type changes from the second to the first type and the status of speculative execution indicates that a result of speculative execution is to be accepted, the logic circuit can reconfigure the second subset when the execution type is the first type; and allocate the at least one cache set when the execution type changes from the first to the second type.

Abstract: A memory management unit of a processor may receive a command associated with a process. The command may specify an operation to be performed by another device. The memory management unit may determine a counter value associated with a shared work queue of the another device, an indication the shared work queue to be specified by the command. The memory management unit may determine whether to accept or reject the command based on the counter value and a threshold for the process.

Abstract: A memory module system with a global shared context. A memory module system can include a plurality of memory modules and at least one processor, which can implement the global shared context. The memory modules of the system can provide the global shared context at least in part by providing an address space shared between the modules and applications running on the modules. The address space sharing can be achieved by having logical addresses global to the modules, and each logical address can be associated with a certain physical address of a specific module.

Abstract: Processing circuitry (4) performs data processing in response to instructions. Memory management circuitry (28) controls access to memory based on page table information capable of associating a given page of memory address space with a read-as-X property indicative that reads to an address in the given page of memory address space should be treated as returning a specified value X. In response to determining, for a read request issued to read a read target value for a read target block of memory address space, that at least part of the read target block corresponds to a page associated with the read-as-X property, the memory management circuitry (28) controls the specified value X to be returned to the processing circuitry (4) as at least part of the read target value. This enables large regions of memory address space to be treated as storing a specified value without needing to commit physical memory for those regions.

Abstract: One example method includes, at a replication data source, initiating a replication process that includes transmitting a replication stream to a replication destination vault, and data in the replication stream is transmitted by way of a closed airgap between the replication data source and the replication destination vault, switching, by the replication data source, from a transmit mode to a receive mode, receiving, at the replication data source, a first checksum of a file, and the first checksum and file were created at the replication destination vault, receiving, at the replication data source, the file, calculating, at the replication data source, a second checksum of the file, and when the second checksum matches the first checksum, ending the replication process.

Abstract: A storage device according to some example embodiments comprises a non-volatile memory including a first memory including a plurality of zones configured to sequentially store data based on a write pointer, the write pointer indicating a position to write the data, and a second memory configured to store preliminary data to be written in the plurality of zones, and a storage controller configured to receive a plurality of operation requests, each of the plurality of operation requests including a logical block address, a write command, and write data, and store first write data corresponding to a first operation request in the second memory as first preliminary data, if the position of a first logical block address corresponding to the first operation request among the plurality of operation requests and the write pointer does not match.

Abstract: Methods, systems, and devices for flexible information compression at a memory system are described. For example, a memory system may compress information in a change log to reduce the frequency of transfers of one or more mappings between volatile memory and non-volatile memory. The memory system may compress information associated with a sequence of sequentially-indexed addresses by storing the information associated with those addresses at a pair of entries in the change log. The memory system may additionally switch between a first operating mode associated with identifying sequentially-indexed addresses and generating compressed entries, and a second operating mode associated with generating entries of the change log for each address received in commands.

Abstract: Methods, systems, and devices for compressed logical-to-physical mapping for sequentially stored data are described. A memory device may use a hierarchical set of logical-to-physical mapping tables for mapping logical block address generated by a host device to physical addresses of the memory device. The memory device may determine whether all of the entries of a terminal logical-to-physical mapping table are consecutive physical addresses. In response to determining that all of the entries contain consecutive physical addresses, the memory device may store a starting physical address of the consecutive physical addresses as an entry in a higher-level table along with a flag indicating that the entry points directly to data in the memory device rather than pointing to a terminal logical-to-physical mapping table. The memory device may, for subsequent reads of data stored in one or more of the consecutive physical addresses, bypass the terminal table to read the data.

Abstract: A system has an unmatched communication architecture for a unidirectional command bus and compensates for drift on the command bus based on data provided on a bidirectional data bus. The memory device has an oscillator to measure drift or an amount of delay for the command bus over a time interval. The memory device can return a value over the data bus to the memory controller based on the delay measured with the oscillator. Based on receiving the value, the memory controller can adjust configuration settings for communication on the command bus.

Abstract: Methods, systems, and devices for techniques for managed NAND translation with embedded memory systems are described. A host system may generate a first command to access a logical memory address associated with a memory system. The host system may identify a physical memory address of the memory system based on generating the first command. The host system may output to the memory system a second command and the physical memory address, where the second command may be communicated to the memory device using a protocol associated with a controller of the memory system. The memory system may then access memory cells in a memory device associated with the physical memory address based on receiving the second command and the physical memory address.

Abstract: A memory access method comprises adding routing information to a memory page table, so that a memory management unit (MMU) queries, in a process of performing address translation on a virtual address (VA), the memory page table to obtain the routing information. After querying the memory page table and obtaining a physical address (PA), the MMU may directly route the PA based on the routing information, whereby a system address decoder (SAD) is not needed for further decoding the PA.

Abstract: Translated addresses of a memory device can be stored in a first LUT maintained by control circuitry. Untranslated addresses can be stored in a second LUT maintained by the control circuitry. In response to a translation request for a particular translated address of the memory device corresponding to a target untranslated address, an index of the second LUT associated with the target untranslated address can be determined, the index of the second LUT can be mapped to an index of the first LUT, and the particular translated address corresponding to the target untranslated address can be retrieved from the first LUT.

Abstract: The present disclosure relates to a shared virtual address space for multi-node computing systems. The shared virtual address space includes a plurality of virtual addresses (e.g. virtual memory pages). A distributed, shared physical memory of the multi-node computing system is formed by combining the physical memory resources of the plurality of nodes. The shared virtual address space enables different nodes of a multi-node computing system to maintain an identical assignment of virtual addresses to physical memory addresses.

Abstract: A variety of applications can include a memory device having dynamic page mapping with compression. The memory device can include a mapping table having an entry location to associate a virtual page with a physical address of a first stripe of data of the virtual page. The entry location can include a flag along with the physical address of the first stripe. The flag can identify data of the virtual page as being compressed or uncompressed. A controller of the memory device, responsive to the flag identifying the data of virtual page being compressed, is structured to generate a format of compressed data of the first stripe with a header. The header can include a count of additional physical addresses to store compressed data of the virtual page and the additional physical addresses. Additional apparatus, systems, and methods are disclosed.

Abstract: Embodiments of this application disclose a memory sharing method and an apparatus. The method in embodiments of this application includes: A host side establishes a first memory page table via a shared virtual address management unit. The first memory page table includes mapping from a virtual address on the host side to a physical address on the host side. A first device side establishes a second memory page table via a shared virtual address agent unit. The second memory page table includes mapping from a virtual address on the first device side to a physical address on the first device side. An agent system memory management unit SMMU on the first device side updates the second memory page table based on the first memory page table, or the host side updates the first memory page table based on the second memory page table.

Abstract: In the present disclosure, a method for improved metadata management includes receiving a memory write command from a host device, performing the data write operation, storing a mapping of the logical address and the physical address as a first logical-to-physical (L2P) address mapping entry of the volatile memory and as a second L2P address mapping entry of the buffer, determining whether a number of the second set of L2P address mapping entries of the buffer exceeds a predefined number of L2P address mapping entries, upon determining that the number of the second set of L2P address mapping entries of the buffer exceeds the predefined number of L2P address mapping entries, sequentially reading the plurality of L2P address mapping tables of the non-volatile memory, and updating the first set of L2P address mapping tables based on the first set of L2P address mapping entries of the volatile memory.

Abstract: A memory control method includes obtaining data parameters in a read queue and a write queue, updating a read/write control strategy according to the first detection result and the second detection result to obtain an updated read/write control strategy, and controlling subsequent read/write operations of a memory according to the updated read/write control strategy. The data parameters correspond to a first detection result of a quantity of data in the read queue and a second detection result of a quantity of data in the write queue. The first detection result is related to a degree of a fullness state of the read queue, and the second detection result is related to a degree of a fullness state of the write queue.

Abstract: Provided in the present application are a data processing method and apparatus, and a device. The method includes: acquiring target decision information corresponding to a capacity physical hard disk; determining a target time instant corresponding to a garbage collection operation based on the target decision information; performing the garbage collection operation on duplicated data in the capacity physical hard disk at the target time instant. Through the technical solution of the present application, the garbage collection operation can be performed at an appropriate time, which prevents the garbage collection operation from preempting a bandwidth of a data read operation, so that the capacity physical hard disk can meet a fast read/write need.

Abstract: A plurality of physical cores of a processor share a memory management unit (MMU) pool comprising a plurality of MMUs. The plurality of MMUs provides each physical core with an address translation function from a virtual address (VA) to a physical address (PA). If an address translation requirement of a physical core is high, for example, when a main memory is concurrently accessed, the plurality of MMUs can serve the physical core.

Abstract: A method for operating a storage system including a storage includes calculating an average length of extents allocated to a logical address region corresponding to a particular node of an address mapping tree, the address mapping tree being associated with the storage, and a mapping information format of the particular node being a first format and, based on the average length, converting the mapping information format of the particular node from the first format to a second format.