Abstract: Methods, systems, and devices for logical-to-physical (L2P) mapping for enhanced granularity data storage are described. A memory system may support write operations according to multiple different write granularities and corresponding data transfer sizes. Entries that map logical addresses to physical addresses within the memory system may include first entries associated with a first data transfer size and second entries associated with a second data transfer size that is greater than the first data transfer size. If the memory system receives a write command that indicates a size of data that is less than or equal to the first data transfer size, the system may update the first entries to indicate a mapping. Data indicated via write commands associated with larger data sizes may be mapped by the second entries. The varying entry structure may support improved write operations and throughput for storage of data at varying granularities.

Abstract: A data decompression apparatus includes a read control circuit, a decompression circuit, and a write control circuit. The read control circuit reads compressed data stored in a first storage area starting from a first address in a random access memory. The decompression circuit decompresses the compressed data in an order from a head to generate decompressed data. The write control circuit, in response to receiving first information specifying data portions to be stored in the random access memory and a second address from the host: transfers the data portions specified in the first information to a second storage area starting from the second address, and outputs a signal indicating that transfer has been completed to the read control circuit. In response to the signal output from the write control circuit, the read control circuit performs control to stop reading the compressed data stored in the first storage area.

Abstract: A method and apparatus for managing a unified virtual memory (UVM) are provided. The UVM is backed by a main processor memory and a coprocessor memory, and the method includes: checking properties of data blocks of the UVM used to execute a deep learning model; based on a first of the data blocks storing weight data of the deep learning model, storing the first data block in the main processor memory among the main processor memory and the coprocessor memory; and performing an operation of the deep learning model based on the first data block using a coprocessor while directly loading at least a portion of the first data block from the main processor memory into a cache memory of the coprocessor without migration of the first data block from the main processor memory to the coprocessor memory.

Abstract: Methods, systems, and devices for cross-temperature measurement of a memory system are described. A memory system may record cross-temperature measurements during operation. For example, the memory system may record, at a first time, a temperature of data stored at the memory system and may compare the recorded temperature at the first time with a write temperature of the data that was recorded at a second time. In some examples, recording the temperature of the data at the first time may be part of performing a read operation or may be part of performing one or more maintenance operations. A difference between the temperature of the data at the first time and the write temperature may be stored at the memory system.

Abstract: The present disclosure describes aspects of free block address management for compressed data storage. In various aspects, a memory controller maintains addresses of free blocks of a memory through a linked list of address storage blocks stored in the memory. An address storage block may include addresses of the free blocks of the memory and an address to a next address storage block of the linked list (e.g., block freelist). As the memory controller writes data to the free blocks of the memory and consumes the addresses stored in the address storage blocks, the memory controller can release the address storage blocks as free blocks. When the free blocks and associated addresses are used up, the remaining address storage blocks are released, and no memory is needed to maintain the list of free blocks. By so doing, the described aspects can reduce free block management overheard and improve memory efficiency.

Abstract: A storage system includes a storage device and a processor. The storage device stores first mapping information and second mapping information. The first mapping information includes information indicating mapping, between an address of a respective volume (VOL) in a respective snapshot family and an address in a respective snapshot virtual device, in each of a plurality of snapshot families each including a primary volume (PVOL) and a secondary volume (SVOL) which is a snapshot of the PVOL. The second mapping information includes information indicating mapping between an address in the respective snapshot virtual device and an address in a deduplication virtual device.

Abstract: A method of operating storage devices, a memory device, a host device, and a switch, is provided. The method includes: receiving, by the memory device, a first request corresponding to target user data from the host device; generating, by the memory device, first input/output (I/O) stream information based on telemetry information corresponding to the storage devices and map data in a buffer memory of the memory device based on the first request, wherein the first I/O stream information indicates a data path between a first storage device of the storage devices and the host device; providing, by the memory device, a first redirection request including the first request and the first I/O stream information to the host device or the first storage device through the switch; and processing the target user data according to the first I/O stream information in the first redirection request.

Abstract: Techniques are provided for combining data block and checksum block I/O into a single I/O operation. Many storage systems utilize checksums to verify the integrity of data blocks stored within storage devices managed by a storage stack. However, when a storage system reads a data block from a storage device, a corresponding checksum must also be read to verify integrity of the data in the data block. This results in increased latency because two read operations are being processed through the storage stack and are being executed upon the storage device. To reduce this latency and improve I/O operations per second, a single combined I/O operation corresponding to a contiguous range of blocks including the data block and the checksum block is processed through the storage stack instead of two separate I/O operations. Additionally, I/O operation may be combined into a single request that is executed upon the storage device.

Abstract: Systems and methods for monitoring memory accesses. A storage system comprises a first memory device, a second memory device, and a controller configured to communicate with the first memory device and the second memory device. The controller is configured to: receive, from a computing device, a first request for first data; identify a first address based on the first request; search the first memory device for the first address; modify a first count maintained in the second memory device for the first address; receive from the computing device a second request; and provide the first count in response to the second request.

Abstract: There is provided an apparatus that includes processing circuitry for performing processing in one of a fixed number of at least two domains. One of those domains is subdivided into a variable number of execution environments and memory protection circuitry uses a key input to perform encryption or decryption on the data of a memory access request issued to a memory address from within a current one of the domains. The key input is different for each of the domains and for each of the execution environments, the key input for each of the domains is fixed at boot time of the apparatus, and the key input for each of the execution environments is dynamic.

Abstract: A processing device in a memory sub-system detects an occurrence of a scan ahead trigger event in a memory sub-system, initiates a scan ahead operation of a plurality of command submission queues in a host system coupled to the memory sub-system to read a plurality of pending command submission queue entries from the plurality of command submission queues, and stores respective indications of the plurality of pending command submission queue entries in a cache memory of the memory sub-system.

Abstract: Large gaps in a L2P table that are disturbed by a few occupied addresses may be efficiently utilized by locating and considering the low-density of these occupied addresses in regards to the large gap (i.e., the gap free region altogether). By identifying a gap in a L2P table and then determining if the number of occupied addresses in the gap are less than a threshold value, the gap with the limited number of occupied addresses may be indicated as available RAM buffers for the system. The limited number of occupied addresses may then be marked and replaced with other addresses to evacuate a longer sequence of free addresses that can be used by the system, thereby optimizing data storage operations. In some embodiments, conventional clustering algorithms may be used to determine gap availability. In some embodiments, the stability several gaps may be tracked and used to determine storage priority.

Abstract: A controller maintains logical block address (LBA) to physical block address (PBA) mappings as mSets in a storage address table (SAT). Because the SAT may include many mappings, and, consequently, have a large size, the SAT may be stored in a distanced memory from the controller, such as a non-volatile memory device of the data storage device or a host memory buffer of a host device that is coupled to the data storage device. In order to optimize performance, a portion of the SAT may be stored as a compressed address table (CAT) in an internal memory of the controller or another volatile memory of the data storage device. During operation, the controller maintains an active range of mSets in the CAT by adding mSets to the CAT based on whether the LBA is sequential to the active range and a hit count of the active range.

Abstract: Data storage devices and methods of operating the data storage devices are discloses. In an embodiment, a storage device may include a memory device including a plurality of super blocks, each super block including a plurality of logical pages to store a plurality of pieces of logical page data and a plurality of parity areas to store a plurality of pieces of corresponding parity data, and a memory controller configured to determine target logical page data among the plurality of pieces of logical page data based on at least one of a read count or an erase count of a first super block, and control the memory device to store first parity data corresponding to the target logical page data in (1) a first parity area allocated to the first parity data and (2) at least a portion of a second parity area allocated to remaining parity data.

Abstract: A method of preloading address translation information directly into cache memory of an IOMMU includes storing the address translation information in a register set of memory management input/output registers of an input-output memory management unit and loading the address translation information into cache memory of the input-output memory management unit. The address translation information includes a virtual address and a corresponding physical address of system memory of a computing system. The address translation information is sent by software being executed by a processor of the computing system. The address translation information is received directly from the processor.

Abstract: A first memory resource is configured to store a data structure. The first memory resource is coupled to a second memory resource that is configured to store a plurality of data structures. A processing device is coupled to the first memory resource, the second memory resource, and a third memory resource. The processing device writes data entries to the data structure within the first memory resource, determine that the data structure within the first memory resource includes a threshold quantity of data entries, and write the contents of the data structure within the first memory resource to a data structure within the second memory resource. The processing resource is further configured to move the contents of the contents of the data structure in the second memory resource to the third memory resource by readdressing the entries written within the second memory resource to virtual addresses associated with the third memory resource.

Abstract: A cache system, having cache sets, a connection to a line identifying an execution type, a connection to a line identifying a status of speculative execution, and a logic circuit that can: allocate a first subset of cache sets when the execution type is a first type indicating non-speculative execution, allocate a second subset when the execution type changes from the first type to a second type indicating speculative execution, and reserve a cache set when the execution type is the second type. When the execution type changes from the second to the first type and the status of speculative execution indicates that a result of speculative execution is to be accepted, the logic circuit can reconfigure the second subset when the execution type is the first type; and allocate the at least one cache set when the execution type changes from the first to the second type.

Abstract: A memory management unit of a processor may receive a command associated with a process. The command may specify an operation to be performed by another device. The memory management unit may determine a counter value associated with a shared work queue of the another device, an indication the shared work queue to be specified by the command. The memory management unit may determine whether to accept or reject the command based on the counter value and a threshold for the process.

Abstract: A memory module system with a global shared context. A memory module system can include a plurality of memory modules and at least one processor, which can implement the global shared context. The memory modules of the system can provide the global shared context at least in part by providing an address space shared between the modules and applications running on the modules. The address space sharing can be achieved by having logical addresses global to the modules, and each logical address can be associated with a certain physical address of a specific module.

Abstract: Processing circuitry (4) performs data processing in response to instructions. Memory management circuitry (28) controls access to memory based on page table information capable of associating a given page of memory address space with a read-as-X property indicative that reads to an address in the given page of memory address space should be treated as returning a specified value X. In response to determining, for a read request issued to read a read target value for a read target block of memory address space, that at least part of the read target block corresponds to a page associated with the read-as-X property, the memory management circuitry (28) controls the specified value X to be returned to the processing circuitry (4) as at least part of the read target value. This enables large regions of memory address space to be treated as storing a specified value without needing to commit physical memory for those regions.