Abstract: The present invention provides an apparatus for signaling that a predetermined time value has elapsed, having a device for acquiring and storing the amplitude value of a clock signal at an acquisition instant in the temporal profile of the clock signal. A device is provided for continuously comparing the acquired and stored amplitude value of the clock signal with an instantaneous amplitude value of the clock signal and for outputting a comparison signal which has a first logic state if the instantaneous amplitude value of the clock signal is less than the stored amplitude value and has a second logic state if the instantaneous amplitude value of the clock signal is greater than the stored amplitude value.

Abstract: The present invention relates to the conversion of signals from RF to baseband using transition functions, or edge functions. These functions typically transition from positive to negative, or from negative to positive, synchronously with the transition of the received pulse signal, effecting detection essentially by synchronously rectifying a signal cycle of the received pulse, producing a net signal at baseband that can be further processed to detect modulation according to the modulation format. It is further disclosed how to configure these systems for optimal reception with a filter optimized for a given detect signal function. Generalizations of the matched filter embodiment lead to further embodiments employing alternative detection functions. Also disclosed is a two-stage version which applies a decode signal to the rectified signal. This step can be performed by a single correlator or by a plurality of correlators in parallel.

Abstract: A dual phase pulse modulation (DPPM) decoder circuit processes a DPPM signal, which is in the form of a series of high and low pulses whose pulse widths represent successive groups of M data bits, so as to recover data carried by the signal. Each of the 2M possible data values of an M-bit group corresponds to one of 2M distinct pulse widths. Circuit blocks determine the width of each pulse by piping the DPPM signal through a short delay chain and inputting the delayed outputs and the non-delayed signal into AND logic gates, whose outputs are used to clock flip-flop registers. The registers are reset to a known state at the start of each signal pulse and toggled to an opposite state if clocked. The registered outputs are interpreted by logic to obtain the corresponding M-bit groups.