Abstract: Circuits and methods for a combined phase detector are provided. In some embodiments, circuits for a combined phase detector are provided, the circuits comprising: a tri-state phase frequency detector and charge pump that receives a reference signal and a first input signal, and that produces a first output signal; and a sub-sampling phase detector that receives the reference signal and a second input signal, and that outputs a second output signal, wherein the first output signal and the second output signal are coupled together.
Type:
Grant
Filed:
July 13, 2012
Date of Patent:
November 24, 2015
Assignee:
The Trustees of Columbia University in the City of New York
Inventors:
Peter R. Kinget, Chunwei Hsu, Shih-An Yu, Karthik Tripurari
Abstract: A rake architecture for a frequency division duplex (FDD) and use also in TDD and TD-SCDMA type communications system, designed to significantly reduce the memory capacity required and thereby also reduce an area on the die of an application specific integrated circuit (ASIC) into which the memory is integrated. A single circular buffer, preferably of the shared memory type is shared by all of the rake fingers of a rake receiver to significantly reduce the hardware and software required to time align multipath signals received by a UE from a base station. This unique time alignment technique also reduces the number of code generators required to track a plurality (typically three) of base stations.
Abstract: The present invention provides an amplifying apparatus including, two amplifiers for receiving input signals in common and for outputting their respective amplified signals, a combiner for combining the output signals of the two amplifiers and for outputting a combined signal, the amplifying apparatus which inhibit the distortion component in the output of amplifiers in the transition state. This amplifying apparatus comprises, a predistortion unit for determining a distortion compensation component based on the output of the combiner and for predistorting the input based on the determined distortion compensation component, and a gain control unit for attenuating the inputs to set lower than in the steady state by reducing the gain in the transition from two amplifier operation to one amplifier operation, or in the transition from one amplifier operation to two amplifier operation, or at the time of removal or attachment the amplifiers.