Abstract: An interface apparatus provides a connection between a host having an IEEE 1394 input/output port and a mass storage device having an ATA input/output port. A receive FIFO and a transmit FIFO within the interface apparatus operates to store small-size packets, or operates to store the buffer address of large-size packets, as the small and large size packets are respectively received from the host or transmitted to the host. In both the host receive and host transmit modes of operation of the interface apparatus, the small-size packets are found in the receive FIFO or the transmit FIFO, whereas the data content of large-size packets is stored in the buffer as the corresponding buffer address is stored in the receive FIFO or the transmit FIFO.

Abstract: A digital data transfer system transfers digital data along a path in a ring topology. The digital data transfer system comprising a host controller and a digital data transfer subsystem. The host controller generates and receiving digital data and the digital data transfer subsystem receives the digital data from the host controller and transferring the digital data to one or more devices connectable thereto, and further receives digital data from the last of the devices connectable thereto for provision to the host controller, thereby to define the ring data transfer topology. The digital data transfer subsystem comprises an upstream port, a plurality of input/output ports and a port control. The upstream port transfers digital data from an external source to the input of the first input/output port in the series and transfers digital data received from the last input/output port in the series to the host controller.

Abstract: A computer system includes a bus system having a local bus unit, a memory bus unit, an input/output bus unit, and an expansion bus unit. A pluggable central processing unit circuit board includes a microprocessor, a pluggable memory circuit board coupled to the central processing unit circuit board through the memory bus unit, and a pluggable bridge circuit board coupled to the central processing unit circuit board. A plurality of connectors includes a first connector unit for receiving the pluggable central processing unit circuit board; a second connector unit for receiving the pluggable memory circuit board; and a third connector unit for receiving the pluggable bridge circuit board. The third connector unit is coupled to the first connector unit of the central processing unit circuit board through the bus system. A plurality of peripheral devices are coupled to the bridge circuit board through the input/output bus unit.

Abstract: An I/O adapter connects an I/O adapter to an I/O bus and includes a device interrupt status register and an interrupt status shadow address register. The device interrupt status register stores the interrupt status of the I/O adapter. The I/O adapter accesses the interrupt status shadow address register to determine an address of main memory at which the device interrupt status register is shadowed. After shadowing the interrupt status, the I/O adapter interrupts the processor complex which may then access local, main memory to determine the interrupt status. A multifunction I/O adapter permits a plurality of I/O adapters to be connected thereto and includes a function interrupt status register to summarize the interrupt status of all the I/O adapters attached thereto. After shadowing the summarized interrupt status, the multifunction I/O adapter interrupts the processor complex which may then access local, main memory to determine the interrupt status.

Abstract: A computer system includes a data storage device on the first data bus, a device on the second data bus, and a bridge device capable of storing multiple data transactions for delivery from the second data bus to the first data bus. The bridge device includes a first data storage buffer preassigned to one of the transactions held in the bridge, and a buffer management element that assigns, if necessary, a second data storage buffer to the data transaction when the data associated with the transaction overflows the first data storage buffer.

Abstract: A signal converter which receives signals from a plurality of sensor terminal ends to detect physical quantities in a plant and conducts a necessary correction for the signals to send the signals to a host computer or which transmits signals from the host computer to operation terminal ends in the plant includes a sensor terminal end amplifier including a processing unit for receiving a signal from a sensor terminal end and conducting a predetermined amplifying operation for the signal and a storage unit in which information items related to the sensor terminal and the processing unit are stored, an operation terminal end amplifier including a converting unit for converting signals into predetermined control signals which can be received by the operation terminal end and a storage unit in which information items related to the operation terminal end and the converting unit are stored, and a signal converting section including a connecting unit for connecting the sensor terminal amplifier section to the operat

Abstract: A method of communication between an adapter and a drive improves the data processing efficiency of the adapter and data transfer efficiency between the adapter and the drive.The drive has a slot to receive a disk cartridge containing a disk and drives the cartridge. The adapter is shaped to be inserted into the slot of the drive. The adapter has a controller to transfer data between the adapter and the drive through the heads thereof. The controller formats data so that the formatted data may fit into at least part of a disk format having tracks and sectors handled by the drive. The controller assigns a specific one of the tracks to the formatted data and transmits the track with the data to the drive.

Abstract: Web pages retrieved by a browser core are translated into user interface component definitions and page information. The definitions and page information are transmitted to a user device which recomposes the definitions and page information into a format for presentation to a user on a user device. Transmitting the definitions and page information includes translation of the definitions and page information into a format appropriate for both the particular communications media on which the information is transmitted, and the device to which the information is transmitted. The device includes a browser client which performs the recomposition. The browser client also receives user input, and may respond by altering the information locally at the user device, and sending information related to the user selection back to the browser core for further processing.

Abstract: A communication protocol employing dummy input and output values is used in communicating blocks of data between an industrial controller and its I/O modules while preventing premature use of partially transmitted data by the I/O modules yet without the need for special handshaking type circuitry or the continuous overhead of such handshaking protocols.

Abstract: In one aspect of the present invention, a bus buffer is provided. The bus buffer includes at least one buffer group having first and second groups of control input terminals. The first and second groups of control input terminals control different operational characteristics of the buffer group. The bus buffer includes first and second capture registers and first and second update registers. The data output terminals of the first update register are connected to the first group of control input terminals. The data output terminals of the second update register are coupled to the second group of control input terminals. The data input terminals of the first and second update registers are coupled to the data output terminals of the first and second capture registers, respectively. The bus buffer includes a new settings register having data output terminals coupled to the data input terminals of the capture registers.

Abstract: Interface circuitry for an integrated circuit is provided, which can operate in accordance with any one of several different protocols. Protocol identifying circuitry within the interface monitors signals passed from a master/host device to the integrated circuit. Based upon the characteristics of the signals, the protocol being used by the master/host device can be determined, and the interface circuitry on the integrated circuit may be configured accordingly. The protocol identifying circuitry "remembers" which protocol is in use, so that the interface circuit remains configured for the correct protocol regardless of subsequent changes in the signals from the master/host device.

Abstract: A computer comprised of a computing system positioned at a first location and a human interface, which includes a video monitor, and plural I/O devices, specifically, a keyboard, mouse and printer, positioned at a second location remotely located relative to the first location. The computer further includes a first encoder coupled to the computer system, a first decoder coupled to the video monitor and the at least one I/O device and a transmission line which couples the encoder to the decoder. The first encoder receives, from the computing system, a video signal to be transmitted to the video monitor and a non-video signal to be transmitted to the at least one I/O device. The first encoder combines the video and the non-video signals into a combined signal and transmits the combined signal to the first decoder via the transmission line.

Abstract: A plurality of CIS1 through CISM are installed in memory of a PC card. Each CIS is provided with basic attribute information and functional attribute information, which are mutually independent, A selection signal for the CIS to be used is input from selection signal input means. A selection signal discriminator determines the CIS selected by means of the signal input from the selection signal input means. A CIS switch setting element sets the designated CIS as the CIS to be read in by a personal computer, and causes the CIS that has been set to be read in by the personal computer.

Abstract: In this device, each processor (P1 to P3) is associated with at least one dressable space (R1 to R3), whereas all the processors and all the addressable spaces are in communication by way of a common communication bus (BC).Between all the processors and each addressable space is connected an intercommunicating connection node (N1 to N3), each connection node including control means (LC, D1, D2) forensuring priority of access of any processor to its own addressable space; andensuring a hierarchy of priority of access to the addressable spaces of the other processors among said plurality of processors.

Abstract: A system and method for reconfiguring a peripheral device connected by a computer bus and port to a host from a first generic configuration to a second manufacturer specific configuration is provided in which the configuration of a peripheral device may be electronically reset. A peripheral interface device for a standardized computer peripheral device bus and port is also provided in which a physical disconnection and reconnection of the peripheral device is emulated to reconfigure the bus and port for a particular peripheral device.

Abstract: An information processing apparatus has a plurality of nodes, a connection line for connection between the plurality of nodes, an arbiter for performing arbitration of use of the connection line, and an arbitration signal line for connection between the arbiter and each node, wherein the arbiter performs processing of a request for use of the connection line and processing of additional information related to data transfer executed after connection of the connection line.

Abstract: Inspection apparatuses of an inspection apparatus group are connected to a network and transfer inspected result to a data collection system. The same wafer selected from a specific process is inspected by the different inspection apparatuses and the inspected data are collected and analyzed to calculate a correlation degree among the inspection apparatuses. On the other hand, the course of occurrence of failures in the same process can be analyzed to thereby calculate an average occurrence frequency of failures. An optimum inspection apparatus and inspection frequency are successively obtained on the basis of calculated results of an inter-apparatus correlation degree calculation process and a failure occurrence frequency calculation process, so that a feeding method of wafers to the inspection apparatus group is indicated through an inspection apparatus group management system.

Abstract: A disk sequencer, which is loaded with control words from a format table and a frame number associated with the first control word loaded, automatically cycles through loaded control words and finds a control word that corresponds to the current position of a data sector. The disk sequencer includes a first counter that is initialized according to a frame number read from a servo sector or according to an index mark and incremented for each end-of-servo pulse so that the first counter accurately indicates the current position of a data head to a data frame granularity. A second counter is loaded with a data frame number associated with the control words, and the second counter is incremented each time the last control word for a data frame is discarded. For automatic alignment, the disk sequencer cycles through and discards control words until comparison of the counts in the two counters indicates the control words are properly aligned.

Abstract: This invention relates to a radio communication terminal having a detachable memory for storing private information and, more particularly, to a terminal designed to manage the private information stored in a memory in the terminal by using a detachable memory. The identification number of the detachable memory mounted in the radio communication terminal in the previous operation is stored in the terminal. In using the radio communication terminal the next time, if the identification number of the detachable memory mounted in the terminal does not coincide with the previous identification number, the private information stored in the memory in the terminal is cleared. In addition, the identification number of a permitted detachable memory is stored in the memory in the terminal to inhibit the use of a memory having an identification number other than the above identification number.

Abstract: A computer program provides for the display of selected portions of two or more records on a display screen where the portions selected are from different records, and may be from different files. Provision is made for scrolling of the full text of the displayed records, which may be grouped by common subject matter.Alternatively one of the two or more records may be displayed on the full screen with the capability for selectively switching between the single record and two or more records or a display showing portions of more than one record from more than one file.