Abstract: Computer software for, computer apparatus for, and a method of automatically generating a user interface for a relational database comprising extracting schema information from the relational database and automatically generating corresponding schema and user interface metadata, storing the metadata in a repository, and automatically developing from the metadata a user interface appropriate to the relational database.

Abstract: In a computer system, a distributed storage system having a data coherency unit for maintaining data coherency across a number of storage devices sharing such data is described. The data coherency unit includes logic to monitor data transition states in each of the data storage devices to detect when the processing status of data being shared by two or more of the storage devices changes. The data coherency unit advantageously ensures a status change in shared data in one storage device is broadcast to other storage devices having copies of the data without having each storage device independently monitor adjourning storage devices to detect data state changes.

Abstract: In general, in one aspect, the disclosure describes a cache that includes interface that receives data access requests that specify respective data storage addresses, a back-end interface that can retrieve data identified by the data storage addresses, cache storage formed by at least two disks, and a cache manager that services at least some of the requests received at the front-end interface using data stored in the cache storage.

Abstract: The 64-bit single cycle fetch method described here relates to a specific ‘megastar’ core processor employed in a range of new digital signal processor devices. The ‘megastar’ core incorporates 32-bit memory blocks arranged into separate entities or banks. Because the parent CPU has only three 16-bit buses, a maximum read in one clock cycle through the memory interface would normally be 48-bits. This invention describes an approach for a fetch method involving tapping into the memory bank data at an earlier stage prior to the memory interface. This allows the normal 48-bit fetch to be extended to 64-bits as required for full performance of the numerical processor accelerator and other speed critical operations and functions.

Abstract: A disk storage system has high throughput between a disk adapter of a disk controller and a disk array. The disk adapter of the disk controller is connected to the disk array through switches. Data on a channel between the switch and a RAID group is multiplexed in the switch to be transferred onto a channel between the switch and the disk adapter and data on the channel between the switch and the disk adapter is demultiplexed in the switch to be transferred onto the channel between the switch and the RAID group. A data transfer rate on the channel between the disk adapter and the switch is made higher than that on the channel.