Abstract: A device with a small number of circuits is provided for blocking illegal address access from a bus master device connected to the processor system bus. An illegal address blocking circuit is inserted into the address line and control lines between the bus master device and the bus or the bus control circuit, according to the system bus configuration. A register is installed within the illegal address access blocking device to set an address range where access is allowed. The address output from the address line is then checked by a comparator to find if it is within the allowable range or not, and if it is outside the allowable range, then that illegal access is prevented by blocking the output on the control line.

Abstract: In the case in which data in a storage system A is remotely copied to a storage system B, it is not taken into account whether the data of the remote copy is WORM data. In the case in which a setting is made such that data stored in a volume in the storage system A is copied to a volume in the storage system B, storage system A judges whether an attribute to the effect that data can be referred to and can be updated or to the effect that data can be referred to but cannot be updated is added to the volume in the storage system A. Then, if the volume is a volume to which the attribute to the effect that data can be referred to but cannot be updated is added, such attribute is added to the volume in the storage system B.

Abstract: A computer system includes a central processing unit (CPU) and a cache memory coupled to the CPU. The cache memory includes a plurality of compressible cache lines to store additional data.

Abstract: An integrated circuit chip is provided having a port for receiving a character string. A hardware hashing circuit on the integrated circuit chip is configured to perform a hashing function on the character string, thereby creating a hashed output value. A binary content addressable memory (CAM) array on the integrated circuit chip is coupled to receive the hashed output value. The binary CAM array provides an index value in response to the hashed output value if the hashed output value matches an entry of the binary CAM array. In a particular embodiment, the hardware hashing circuit can be configured to process character strings having different lengths (greater than the width of the binary CAM array) in response to one or more configuration bits. The hardware hashing circuit can include, an input register, Data Encryption Standard (DES) circuitry and exclusive OR circuitry.

Abstract: A static random-access memory (SRAM) provides volatile storage of data in a cellular telephone. Connected to the volatile SRAM is a second SRAM that provides nonvolatile storage of data by backup battery means. Writing and reading of either volatile or nonvolatile data can occur. Additionally, provision is made to automatically back up data written to the volatile SRAM in the nonvolatile SRAM, as well as to streamline restoration of backed-up data from the nonvolatile SRAM to the volatile SRAM.

Abstract: Cache sharing for a chip multiprocessor. In one embodiment, a disclosed apparatus includes multiple processor cores, each having an associated cache. A control mechanism is provided to allow sharing between caches that are associated with individual processor cores.

Abstract: A method and apparatus for satisfying load operations by accessing data from a store buffer is described herein. It is a further goal of the present invention to satisfy load operations faster than prior art techniques in most cases. Finally, it is a goal of the present invention to provide an improved technique for satisfying load operations that does not significantly impact processor performance in the event that a present load is not satisfied within a predetermined amount of time.

Abstract: A method and system for storing arranged data in a memory, the system including: (a) a plurality of random access memories, each random access memory (RAM) of the plurality including: (i) a first array of cells, the first array having at least two dimensions and having rows and columns, the first array designed and configured to contain a plurality of key entries, each of the cells having a unique address including a row index and a column index, each of the key entries for matching with an input key, and (b) a processor designed and configured to search the plurality of key entries for a match, in response to the input key, the plurality of RAMs designed and configured such that: (i) at least one row in a second of the RAMs has a row index that is identical to a row index in a first of the RAMs, and (ii) the key entries are arranged within each of the plurality of RAMs in monotonic order.

Abstract: One embodiment of the present invention provides a system for mapping memory addresses to cache entries. The system operates by first receiving a memory request at the cache memory, wherein the memory request includes a memory address. The system then partitions the memory address into a set of word offset bits and a set of higher-order bits. Next, the system maps the memory address to a cache entry by computing a modulo operation on the higher-order bits with respect to an integer and using the result as the cache index.

Abstract: A flash memory configuration and access method having a particular conversion method that uses the page or the sector in each flash memory block instead of the block that is commonly used as the base of the data conversion storage to store data. When data is written into the physical flash block of the flash memory, the original logic sector information can be preserved. The data is written into the same block of the flash memory in a manner according to the sequence as it is received instead of the sequence of the logic sector. Therefore, the block position does not move to refresh the block content until the physical block is full. Consequently, the number of times to move the physical block of the flash memory can be reduced to increase the lifetime of the flash memory. Moreover, since the number of times to erase is reduced, so that the writing speed can speed up to improve the operation efficiency.

Abstract: A system and method provides active inheritance on memory writes such that entities issuing later writes ensure that the effects of earlier writes to the same memory block will be seen. A write chain is preferably formed by storing information and state in miss address file (MAF) entries maintained by the entities. The write chain links the entities requesting write access to the memory block. When the desired memory block becomes available, the information and state stored at the MAF entries is then utilized by each entity in ensuring that all earlier writes are complete before its write is allowed to complete.

Abstract: In a disk control device arranged to include a CPU, a plurality of channel control units, a plurality of disk control units, a cache memory, and a data transfer integrated circuit communicably connected to the cache memory via a plurality of data buses, when receiving a request for access to the cache memory from any one of the CPU, the channel control units and the disk control units, the data transfer integrated circuit provides access to the cache memory by use of a certain number of one or ones of the data buses, which number is determinable in accordance with a transfer data length that is set in the access request.

Abstract: A method of passing a location of a data interface. The method involves storing a first pointer in an architected location for locating information related to a system firmware read only memory (ROM). A portion of memory is allocated for a data structure that is an interface for handing off system component information. A second pointer is stored in a memory location pointed to by the first pointer. The second pointer points to the data structure.

Abstract: A method, system and computer readable medium for a computer-automated method for identifying given image data, including obtaining template image data corresponding to said given image data; calculating correlation values between the given image data and said template image data; and identifying said image data based on the correlation values calculated in the calculating step.

Abstract: A method of inspecting an automotive wheel includes providing an inspection station having a light source for illuminating the wheel, and a camera having a zoom lens. The automotive wheel is positioned in the inspection station and the wheel is illuminated to generate a first image including the reference feature. After the first image information has been delivered to the processor, the model of the automotive wheel is determined on the basis of data stored in the processor and the parameters to be used during the inspection of the particular model are employed in the subsequent inspection. The processor determines the position of the reference feature and determines whether the automotive wheel is in the desired position. If not, the wheel is rotated to move the reference feature toward the desired position.

Abstract: A distance measurement apparatus of the present invention outputs image signal from the area sensor to which an optical image is input from a plurality of distance measurement areas two-dimensionally distributed in an area to be shot. A calculation control circuit detects portions changing equally to or more than a predetermined value in positive or negative directions, for the output level of pixel rows arranged on a plurality of straight lines included in the image signal. The distance measurement area is identified, based on the output of this calculation control circuit.

Abstract: An optical axis direction, a distance measurement accuracy and so on are efficiently performed for quality assurance of a vehicle-mounted camera in cooperation of an image processing unit and a vehicle-mounted navigation control unit. In a vehicle monitoring system for imaging view ahead of the vehicle with the camera (2a, 2b) installed in the vehicle body and for recognizing a running condition with the image processing unit (20), the image processing unit measures an optical axis direction and a distance measurement accuracy to determine whether the camera quality is appropriate or not for quality assurance of the vehicle-mounted camera. The determined result is displayed on a monitor (52) of the vehicle mounted navigation control unit (5) to recommend adjustment of the camera.

Abstract: Error addition section 201 generates correction data by adding correction value Emo and correction value E1 to the input data. Binary processing section 202 converts the correction data to binary data to generate output data. Binary error calculation section 203 calculates binary error E based on the correction data and output data. Propagation coefficient judgment section 204 judges propagation coefficients K1 to K4. Propagation error operation section 205 operates on binary error E and propagation coefficients K1 to K4 to calculate correction value E1 and correction value Emi. Error memory 206 temporarily stores correction value Emi, and outputs it to error addition section 201 when the pixel data to be corrected is input.

Abstract: A system and method for using a machine vision system to locate and register patterns in an object using range data is provided. The machine vision system includes an acquisition system for acquiring a range image of an object. The system also includes a machine vision search tool coupled to the acquisition system for locating an instance of a trained pattern in the image. The tool registering the trained pattern transformed by at least two translational degrees of freedom and at least one non-translational degree of freedom with respect to an image plane. The acquisition system preferably includes a three-dimensional camera.

Abstract: An image processing system and method employs a registration processor (130) to calculate a statistical measure of likelihood for two volumetric images (110, 112). The likelihood is calculated based on an assumption that the voxel values in two images in registration are probabilitically related. The likelihood is calculated for a plurality of relative transformations in iterative fashion until a transformation that maximizes the likelihood is found. The transformation that maximizes the likelihood provides an optimal registration and the parameters for the optimized transform are output to memory (150) for use by a display system (160) in aligning the images for display as a fused or composite image. If statistics about the relationship between the involved images are known, a mutation probability can be derived and used in the likelihood calculation. If there is no such prior knowledge, the mutation probability can be estimated purely from the image data.