Abstract: In an integrated circuit, a stack of thin film layers comprising respectively a bottom electrode, a thin film of metal oxide, a top electrode, a lower barrier-adhesion layer, a hydrogen barrier layer, and an upper barrier-adhesion layer are patterned to form a memory capacitor capped with a self-aligned hydrogen barrier layer. Preferably, the top and bottom electrodes comprise platinum, the metal oxide material comprises ferroelectric layered superlattice material, the upper and lower barrier-adhesion layers comprise titanium, and the hydrogen barrier layer comprises titanium nitride. The hydrogen barrier layer inhibits diffusion of hydrogen, thereby preventing hydrogen degradation of the metal oxides. Part of the upper barrier-adhesion layer is removed in order to increase the electrical conductivity in the layer. Preferably, the memory capacitor is a ferroelectric nonvolatile memory. Preferably, the layered superlattice material includes strontium bismuth tantalate or strontium bismuth tantalum niobate.

Abstract: In one aspect, the invention encompasses a LOCOS process. A pad oxide layer is provided over a silicon-comprising substrate. A silicon nitride layer is provided over the pad oxide layer and patterned with the pad oxide layer to form masking blocks. The patterning exposes portions of the silicon-comprising substrate between the masking blocks. The masking blocks comprise sidewalls. Polysilicon is formed along the sidewalls of the masking blocks. Subsequently, the silicon-comprising substrate and polysilicon are oxidized to form field oxide regions proximate the masking blocks. In another aspect, the invention encompasses a semiconductive material structure. Such structure includes a semiconductive material substrate and at least one composite block over the semiconductive material substrate. The composite block comprises a layer of silicon dioxide and a layer of silicon nitride over the layer of silicon dioxide. The silicon nitride and silicon dioxide have coextensive opposing sidewalls.

Abstract: A process is disclosed for fabricating a transistor having a channel length that is smaller than lengths resolvable using common photolithography techniques. A gate oxide layer is formed over a lightly doped semiconductor substrate. A gate conductor layer is then deposited over the gate oxide layer. The upper surface of the gate conductor layer includes a future conductor area laterally bounded by a spaced pair of target areas, wherein the lateral distance between the spaced pair of target areas is preferably chosen at the photolithography threshold. Nitrogen is implanted into the spaced pair of target areas to form a spaced pair of nitrogen bearing regions within the gate conductor layer, thereby defining a nitrogen free region in the gate conductor layer. A thermal anneal reduces the width of the nitrogen free region. A variable thickness oxide layer is then grown over the entire semiconductor topography and anisotropically etched to form an oxide mask over the reduced-width nitrogen free region.

Abstract: An electronic material is expressed by the composition formula M.sub.Ia M.sub.IIb O.sub.c (where a, b and c are compositions in atomic %, M.sub.I is at least one sort of noble metal selected from the group consisting of Pt, Ir, Ru, Rh and Pd, and M.sub.II is at least one sort of transition metal selected from the group consisting of Hf, Ta, Zr, Nb, V, Mo and W) having a composition within the range of 90.gtoreq.a.gtoreq.40, 15.gtoreq.b.gtoreq.2, 4.ltoreq.c and a+b+c=100. A dielectric capacitor comprises: a diffusion preventing layer made of the material expressed by the composition formula M.sub.ia M.sub.IIb O.sub.c ; a lower electrode on the diffusion preventing layer; a dielectric film on the lower electrode; and an upper electrode on the dielectric film. Another dielectric capacitor comprises: a diffusion preventing layer made of a material expressed by the composition formula M.sub.Ia M.sub.IIb O.sub.c (where a, b and c are compositions in atomic %, M.sub.