Abstract: A data transfer apparatus includes a plurality of channels and a transfer speed control circuit. A plurality of channels are connected to input/output devices, respectively. Each channel is assigned a corresponding channel number. The transfer speed control circuit is arranged between the channels and a memory. The transfer speed control circuit includes a monitor for monitoring a rate of data transfer from the input/output devices to the memory, and a controller for controlling and decreasing a difference in speed between data sent from the input/output devices and memory access when the monitor result represents a predetermined difference.