Abstract: A multilayer substrate provides predetermined connections to and between a plurality of integrated circuit chips mounted thereon. A plurality of layers mounted on a surface of a substrate has a plurality of layers comprising a plurality of dielectric layers, a first plurality of metallic layers, and a second plurality of metallic layers. The first plurality of metallic layers has a predetermined pattern for forming the predetermined connections, these being the x-lines and y-lines. Each of the second plurality of metallic layers provides a predetermined voltage level to the integrated circuit chips, and each of the second metallic layers has a screen-like structure. Each of the first and second metallic layers is insulated from the other metallic layers by one of the dielectric layers, except for desired interconnections between the x-lines y-lines, and power layer (or power plane).
Type:
Grant
Filed:
March 28, 1986
Date of Patent:
October 29, 1991
Inventors:
Boris Plesinger, Lynn H. Brown, Edward D. Pisacich
Abstract: A method of bonding metallic wires, such as strain gages, thermocouples, etc., directly onto ceramic components, such as silicon nitride or silicon carbide turbine parts, by means of a refractory cement formed from a mixture of water, sodium silicate, and a ceramic powder, preferably of a composition similar to the underlying ceramic component. Several thin layers of the mixture are applied and cured so as to provide a strong bond having good thermal shock resistance for testing at typical gas turbine operating temperatures, such as 2500.degree. F. or above.
Abstract: Disclosed herein are electroconductive iron oxide particles having a volume resistivity less than 5.times.10.sup.6 .OMEGA.-cm, and comprising iron oxide particles selected from hematite and maghemite, and SnO.sub.2 particles containing Sb as a solid solution deposited on the surfaces of the iron oxide particles, and a process for producing the same.