Abstract: In a logic simulator for simulating a logic circuit model which is operable in response to first through k-th input logic signals where k is a natural number greater than unity, the first through k-th input logic signals are read out of a memory to simultaneously carry out first through k-th simulations of the logic circuit model and to simultaneously produce first through k-th simulation result signals. The simulation result signals are compared with one another to detect an event different from a normal event and to carry out further simulations in connection with the different event. When the model is assorted into first through last ranks, the simultaneous simulations proceed from the first rank to the last rank one by one. A plurality of faults can also be simultaneously simulated by the logic simulator with a single one of the input logic signals set to the model.