Abstract: The invention disclosed is useful in an I/O system of a programmable controller and provides a method and circuitry by which control and diagnostic information is exchanged between a control unit of an I/O module and a plurality of input/output points thereof. A control signal is generated in the control unit in the form of sequential pulse frames such that the control information is defined by a series of pulse width modulated pulses. Each frame includes a no-pulse time period following the review of pulses to mark the end of a frame. Each I/O point receives a control signal of its own and generates a clock pulse in response to each pulse. The clock pulse initiates a sampling of the corresponding pulse and simultaneously initiates return of a diagnostic signal value to the central unit. Thus, the control signal provides for sampling of its own content and provides for a return of a diagnostic data bit for each control bit.

Abstract: External interface control circuitry is described that couples a microcomputer system (100) to an external device (800). The control circuitry includes a microcomputer (102), a power switch (108) for applying power to the external device (800) in response to a PSC* signal, bus control (104) for gating interface signals from the microcomputer (102) with a PD* signal for application to the external device (800) and a peripheral interface adapter (106) for producing the PC and PD* signals and coupling the PI* and READY*/IRQ* signals to the microcomputer (102). A power-up sequence is executed by the microcomputer (102) in response to grounding the PI* signal when the external device (800) is plugged into the microcomputer system (100). Next, the external device (800) produces a binary zero state of the READY*/IRQ* signal, and in response microcomputer (102) produces a binary one state of the PD* signal and thereafter the PC signal.

Abstract: A vector instruction which designates calculation of vector data or vector data transfer between vector registers and the main memory, is arranged in such a way as to specify an element in the vector register from which the read/write operation is to be commenced, in order to make it possible to start the reading or writing of the vector data stored in the vector register from any desired element, thereby allowing a partial reference to the array data to be made on the vector register. Further, a vector instruction, which designates the vector data transfer between each vector register and the main memory, is arranged in such a way as to be able to specify the number of vector data elements to be transferred, thereby allowing transfer of elements requisite and adequate for a plurality of partial references on the vector register.

Abstract: Apparatus and method for reconfiguring a memory in a data processing system to increase the rate of information transfer between system memory and processor. The system memory is comprised of a plurality M of memory banks, each having a separate data output path. In a first configuration a memory controller addresses the memory banks sequentially to read from one address location at a time. The memory is reconfigured by an address translator providing addresses addressing M banks in parallel, so that M locations are read in each read operation, and a bus reconfiguration multiplexer which reconfigures the bank output busses in parallel and selects one or more bank output busses as the memory output to the system processor.

Abstract: A memory system for storing and retrieving data sequences of symbols in response to a query sequence is disclosed. Each of the sequences is made up of three types of symbols, constants, delimiters, and variables. A data sequence is retrieved in response to a query sequence if the two sequence can be made identical by replacing the variables in each sequence by constants or combinations of constants and delimiters, the combinations beginning and ending with a delimiter. To reduce the time needed to search the memory for all data sequences corresponding to a given query sequence, multiple processing units are employed. In addition to carrying out rule-based searches, the memory system can efficiently retrieve all records containing a specified list of key words.

Abstract: A fail memory equipment has a plurality of memory blocks which can be changed in their combinations serially or in parallel in accordance with the capacity of a memory to be tested, the number of channels to be tested simultaneously and the testing speed. The single fail memory equipment operates in an interleave fetching mode for a high speed test, in a parallel fetching mode for a multi-channel test or in a serial fetching mode for testing a memory of a large capacity, thereby realizing a high speed test, a large capacity memory test and a simultaneous multi-channel test.

Abstract: In order to allow fast execution of branch instructions even with the possibility of branching to different target instructions from the same branch instruction, a target instruction storage provides the target instruction in response to the branch instruction address and address data associated with a target instruction address.

Abstract: A microcomputer including a functional element for executing an internal reset instruction within the microcomputer, without a usual external reset signal. The internal reset instruction is executed every time a usual power-off instruction is executed. Thus, a power-off signal responding to the power-off instruction is maintained as it is by execution of the internal reset instruction. The microcomputer further includes a functional element for maintaining at least the level of a power-off signal until the power is completely cut off.

Abstract: A data processing apparatus comprises a plurality of sub-systems each including at least one arithmetic unit, a plurality of registers, a first selector for receiving vector data and selectively outputting the input data to the registers, and a second selector for receiving the vector data from the registers and selectively outputting the input data to a plurality of output lines. The data output of the arithmetic unit in each sub-system is supplied to the first selector in the same sub-system and the first selector in another sub-system, and the arithmetic unit in each sub-system receives the output data from the second selector in the same sub-system. The data output from the second selector in at least one sub-system is supplied to a main storage unit, and the data output from the main storage unit is supplied to the first selector in at least one sub-system.

Abstract: A plurality of intelligent work stations are provided access to a shared memory through a switching hierarchy including a first array of mapping boxes for receiving a first address from an intelligent work station and including a virtual address and offset and for converting the virtual address into a terminal switch port designation and logical address, a first switch for forwarding the logical address and offset to the designated terminal switch port, a second array of mapping boxes for receiving the logical address and offset and for converting the logical address into a memory switch port designation and physical address, and a second switch for forwarding the physical address and offset to the designated memory switch port as an address to the shared memory.

Abstract: A system for controlling the transfer of a data message over a common communication channel between a plurality of processing devices includes a MOS/LSI controller chip associated with each processing unit for constructing a message to be sent to a sending device acknowledging the receipt of the message and the validity of the message. Logic circuits are included which generate a predetermined sequence of two binary bits indicating the receipt of the message and the validity of the receiving message. The binary bits are framed by two other binary bits and the sequence repeated a predetermined number of times to construct an acknowledgment message. The controller chip further includes logic circuits for decoding the acknowledgment message.

Abstract: An interface circuit for a programmed controller disposed between the CPU of the programmed controller and an input/output unit includes eight N.times. 1-bit RAMs with simultaneous operating switching circuits for accessing the RAMs in parallel by the input/output unit and with sequential operating selecting circuits for accessing the RAMs serially by the CPU, whereby the interfacing process is sped up.

Abstract: A computing system using a syntactic device for chain calculations with displaying an intermediate result to monitor the progress of the calculation is provided. In one embodiment, if an operator wants to take sine of a result of calculations, the operator needs only type "SIN( )" to obtain the answer. The empty parenthesis dilimits a null subexpression, which the computing system, using the syntectic device, interprets as the result function.

Abstract: Disclosed is a data input/output unit which is equipped with a control device (1), a tape puncher (5), a tape reader (4) and a printer (6), and which is capable of operating even in response to a command from a host computer. The printer (6) is provided with a tab set counter (6ca) for setting a number of spaces. A number equivalent to a predetermined number of spaces is added to a print number set in a bit counter (6cc) of the printer (6) and space print data indicative of a prescribed number of spaces is successively set at the beginning of print data for a line to be printed in a print character register (6cg), thereby making it possible to maintain a predetermined space at the left margin on printing paper.

Abstract: The present invention is circuitry which is employed with a data terminal which data terminal in turn is part of a system including a main data processor. The present circuitry includes a microprocessor which is connected to the main data processor and to the keyboard. The microprocessor processes signals from both the main data processor and the keyboard. The system has a plurality of operational function circuits, such as a circuit to effect smooth scrolling on a data display means. There is logic circuitry connected between the microprocessor and the operational function circuits. The logic circuitry provides a first path which permits signals, generated in response to instructions from the main data processor, to pass therethrough to select one of the operational function circuits and simultaneously therewith to turn the selected circuit either on or off.