Abstract: According to one embodiment, a method includes forming first and second gate patterns each including a structure stacked in order of a first insulating layer, a floating gate layer, a charge trap layer, a second insulating layer and a dummy layer on a semiconductor layer, implanting impurities in the semiconductor layer by an ion implantation using the first and second gate patterns as a mask, forming a third insulating layer on the semiconductor layer, the third insulating layer covering side surfaces of the first and second gate patterns, and forming first and second concave portions, the first concave portion formed by removing the dummy layer of the first gate pattern, the second concave portion formed by removing the dummy layer, the second insulating layer, the charge trap layer and the floating gate layer of the second gate pattern.

Abstract: A semiconductor device and method of forming. According to one embodiment, the method includes providing a substrate with defined device regions and having an interface layer thereon, depositing a first high-k film on the interface layer, and performing a heat-treatment to form a modified interface layer. The method further includes depositing a first threshold voltage adjustment layer, removing the first threshold voltage adjustment layer from the second device region, depositing a second high-k film above the first high-k film, and depositing a gate electrode film on the second high-k film. A first gate stack is defined that contains the modified interface layer, the first high-k film, the first threshold voltage adjustment layer, the second high-k film, and the gate electrode film, and a second gate stack is defined that contains the modified interface layer, the first high-k film, the second high-k film, and the gate electrode film.

Abstract: An organic light emitting diode (OLED) display includes: a substrate; a first electrode on the substrate; a first emission layer on the first electrode; a second emission layer on the first emission layer; a second electrode on the second emission layer; and a light emitting assistance layer selectively positioned between the first emission layer and the second emission layer.

Abstract: A semiconductor device includes an oxide semiconductor film including a pair of first regions, a pair of second regions, and a third region; a pair of electrodes in contact with the oxide semiconductor film; a gate insulating film over the oxide semiconductor film; and a gate electrode provided between the pair of electrodes with the gate insulating film interposed therebetween. The pair of first regions overlap with the pair of electrodes, the third region overlaps with the gate electrode, and the pair of second regions are formed between the pair of first regions and the third region. The pair of second regions and the third region each contain nitrogen, phosphorus, or arsenic. The pair of second regions have a higher element concentration than the third region.

Abstract: A light-emitting device and a method of manufacturing the same are provided. The light-emitting device includes a compound semiconductor structure having a first N-type compound semiconductor layer, an active layer, and a P-type compound semiconductor layer, a P-type electrode layer that is disposed on the P-type compound semiconductor layer and electrically connects with the P-type compound semiconductor layer, a plurality of insulation walls disposed at two sides of the compound semiconductor structure and the P-type electrode layer, a plurality of N-type electrode layers penetrating the plurality of insulation walls, and a conductive substrate on which a plurality of N-type electrode connecting layers respectively corresponding to a plurality of N-type electrode layers are separated from a P-type electrode connecting layer corresponding to the P-type electrode layer.

Abstract: Provided are semiconductor device cells, methods for forming the semiconductor device cells and a layout style for the semiconductor device cells. The device cells may be repetitive cells used throughout an integrated circuit. The layout style utilizes an area at the polysilicon level that is void of polysilicon and which can accommodate conductive leads therein or thereover. The conductive leads are formed of material typically used for contacts or vias and are disposed beneath the first metal interconnect level which couples device cells to one another. The subjacent local conductive leads may form subjacent signal lines allowing for additional power mesh lines to be included within the limited number of metal tracks that can be accommodated within a device cell and in accordance with metal track design spacing rules.

Abstract: A semiconductor device is provided, which includes an annular insulation separation portion penetrating a semiconductor substrate, and an electrode penetrating the semiconductor substrate in a region surrounded by the annular insulation separation portion, wherein the insulation separation portion includes at least a first film that gives compressive stress in a depth direction on the side of a substrate, a second film that gives tensile stress in the depth direction is formed on the first film, and film thicknesses of the first and second films are adjusted so that the compressive stress and the tensile stress are almost balanced.

Abstract: A semiconductor module includes a semiconductor having a semiconductor substrate, a first electrode formed on one surface of the semiconductor substrate, and a second electrode formed on an opposite surface of the semiconductor substrate. A first conductive member is in contact with the first electrode. A second conductive member is in contact with the second electrode. A third conductive member is in contact with the second conductive member and extends along the first conductive member. An insulating member provides insulation between the first conductive member and the third conductive member. The third conductive member is fixed to the first conductive member and the second conductive member by being sandwiched between the first conductive member and the second conductive member. The semiconductor device is fixed to the first conductive member and the second conductive member by being sandwiched between the first conductive member and the second conductive member.

Abstract: A photoelectric conversion device includes a film that covers the photoelectric conversion part and a transfer gate electrode, wherein a first region having a refractive index lower than refractive indices of the film and the photoelectric conversion part, is provided between the film and the photoelectric conversion part, and a second region having a refractive index lower than the refractive indices of the transfer gate electrode and the film, is provided between the film and the top surface of the transfer gate electrode, and wherein T1<T2<?/2?T1 is satisfied, where an optical thickness of the first region is T1, an optical thickness of the second region is T2, and a wavelength of a light incident on the photoelectric conversion part is ?.

Abstract: A gate lead wiring and an electrical conductor connecting the gate lead wiring to a protective diode are arranged in a straight line without bending along one and the same side of the chip. A first gate electrode layer extending on the gate lead wiring and the electrical conductor, which connects them to the protective diode, has one bent portion or no bent portion. Further, the protective diode is arranged adjacent to the electrical conductor or the gate lead wiring, and a portion of the protective diode is arranged in close proximity to a gate pad portion.

Abstract: Methods and apparatus for a backside illuminated (BSI) image sensor device are disclosed. A BSI sensor device is formed on a substrate comprising a photosensitive diode. The substrate may be thinned at the backside, then a B doped Epi-Si(Ge) layer may be formed on the backside surface of the substrate. Additional layers may be formed on the B doped Epi-Si(Ge) layer, such as a metal shield layer, a dielectric layer, a micro-lens, and a color filter.

Abstract: A solid-state image sensing device has a unit pixel containing a photoelectric conversion element for detecting a light to generate photoelectrons and pixel drive circuits for driving the unit pixel. The photoelectric conversion element has a photogate structure, and the pixel drive circuits apply a voltage selected from three voltages to the photogate of the photoelectric conversion element to generate or transfer the photoelectrons. The three voltages include at least a first voltage, a second voltage higher than the first voltage, and a third voltage higher than the first voltage and lower than the second voltage.

Abstract: A method for patterning a plurality of features in a non-rectangular pattern on an integrated circuit device includes providing a substrate including a surface with a first layer and a second layer. Forming a plurality of elongated protrusions in a third layer above the first and second layers. Forming a first patterned layer over the plurality of elongated protrusions. The plurality of elongated protrusions are etched to form a first pattern of the elongated protrusions, the first pattern including at least one inside corner. Forming a second patterned layer over the first pattern of elongated protrusions and forming a third patterned layer over the first pattern of elongated protrusions. The plurality of elongated protrusions are etched using the second and third patterned layers to form a second pattern of the elongated protrusions, the second pattern including at least one inside corner.

Abstract: A FinFET comprises an isolation region formed in a substrate, a cloak-shaped active region formed over the substrate, wherein the cloak-shaped active region has an upper portion protruding above a top surface of the isolation region. In addition, the FinFET comprises a gate electrode wrapping the channel of the cloak-shaped active region.

Abstract: A bidirectional switching device includes a semiconductor multilayer structure made of a nitride semiconductor, a first ohmic electrode and a second ohmic electrode which are formed on the semiconductor multilayer structure, and a first gate electrode and a second gate electrode. The first gate electrode is covered with a first shield electrode having a potential substantially equal to that of the first ohmic electrode. The second gate electrode is covered with the second shield electrode having a potential substantially equal to that of the second ohmic electrode. An end of the first shield electrode is positioned between the first gate electrode and the second gate electrode, and an end of the second shield electrode is positioned between the second gate electrode and the first gate electrode.

Abstract: A semiconductor device includes a first conduction-type semiconductor substrate, a first semiconductor region of a first conduction-type formed on the semiconductor substrate, a second semiconductor region of a second conduction-type formed on a surface of the first semiconductor region, a third semiconductor region of the second conduction-type formed to be separated from the second semiconductor region on the surface of the first semiconductor region, a fourth semiconductor region of the second conduction-type formed to be separated from the second semiconductor region and the third semiconductor region on the surface of the first semiconductor region, and a first electrode connected to the second semiconductor region and the third semiconductor region.

Abstract: A method, and an apparatus formed thereby, to construct shallow recessed wells on top of exposed conductive vias on the surface of a semiconductor. The shallow recessed wells are subsequently filled with a conductive cap layer, such as a tantalum nitride (TaN) layer, to prevent or reduce oxidation which may otherwise occur naturally when exposed to air, or possibly occur during an under-bump metallization process.

Abstract: The present invention provides a solid-state imaging device in which high S/N is achieved. A solid-state imaging device includes a photodiode, a transfer transistor, a floating diffusion, a floating diffusion wiring, an amplifying transistor, a power line, and first output signal lines, in which the first output signal lines are formed one on each side of the floating diffusion wiring in a layer having the floating diffusion wiring formed on a semiconductor substrate, and the power line is formed above the floating diffusion wiring.

Abstract: Disclosed are methods for manufacturing a floating gate memory device and the floating gate memory device thus obtained. In one embodiment, a method is disclosed that includes providing a semiconductor-on-insulator substrate, forming at least two trenches in the semiconductor-on-insulator substrate, and, as a result of forming the at least two trenches, forming at least one elevated structure. The method further includes forming isolation regions at a bottom of the at least two trenches by partially filling the at least two trenches, thermally oxidizing sidewall surfaces of at least a top portion of the at least one elevated structure, thereby providing a gate dielectric layer on at least the exposed sidewall surfaces; and forming a conductive layer over the at least one elevated structure, the gate dielectric layer, and the isolation regions to form at least one floating gate semiconductor memory device.

Abstract: A laterally-diffused metal-oxide-semiconductor (LDMOS) transistor includes a first well of a first conductivity type, a source of a second conductivity type formed in the first well, a drift region of the second conductivity type formed in the first well, and a second well of the second conductivity type formed in the first well and below the drift region. The drift region is separated from the source. The LDMOS transistor further includes a drain of the second conductivity type formed in the drift region, and includes a concentrator of the second conductivity type formed in the drift region and separated from the drain. A distance between the concentrator and the source is less than a distance between the drain and the source.