Abstract: A microcomputer is adapted to act as a communications processor for a personal computer of the type having its address and data busses supplied to a female connector forming part of a system expansion slot. The communications processor is formed on a printed circuit card and includes at least two I/O ports, one connected to its edge connector for insertion into the slot connector of the personal computer, and the other formed on its rear edge so as to be accessible to external connectors. The communications processor has a power supply energized through a connector on its rear edge and a back-up battery power supply. The communication processor can receive communications from and transmit to remote sources while the personal computer is being used for other purposes. Receiver messages are stored in the RAM of the communications processor and are unloaded to the personal computer under control of its keyboard at the operator's convenience.

Abstract: A "write-shared" cache circuit for multiprocessor systems maintains data consistency throughout the system and eliminates non-essential bus accesses by utilizing additional bus lines between caches of the system and by utilizing additional logic in order to enhance the intercache communication. Data is only written through to the system bus when the data is labeled "shared". A write-miss is read only once on the system bus in an "invalidate" cycle, and then it is written only to the requesting cache.

Abstract: A data processing system which executes two instruction sequences in an order determined in advance. With the aid of instructions, a main memory common to both sequences is activated for data information reading/writing. Increased data handling capacity is achieved in the following manner: both sequences are executed in parallel to start with. During execution of the first sequence, the main memory is prevented from being activated for writing due to the second sequence write instructions. A write address and data information included in a write instruction associated with the second sequence are intermediately stored. The intermediately stored write address is compared with the read addresses of the second sequence, and data information is prevented from being read from the main memory in response to an identity of the addresses, the intermediately stored data information being read instead.

Abstract: In an input/output process device for controlling data transfer between a central processing unit and an input/output device through a channel by use of any of a plurality of input/output control devices connected to the input/output device, a memory unit is disposed so as to store information representing the address of the input/output control device in association with an identification number of the channels connected to the input/output control device. When selecting the channel for data transfer, the input/output process device reads out the information representing the address of the input/output control device from the memory unit and generates the address for the input/output control device on the basis of the information read out.

Abstract: A skip table is prepared from which a state of a subsequent symbol string and an address of one or plural symbols to be subsequently inputted can be readily determined by making reference to a set of a current symbol string search state and one or plural symbols to be subsequently inputted of the symbol string. When executing searching for the symbol string, data stored in the skip table are looked up to assure the symbol string search by inputting only a minimized number of necessary characters of the symbol string. Necessity of inputting all the characters of the symbol string for searching is eliminated and the processing speed can be increased considerably. A plurality of symbol strings may be searched for.

Abstract: A task control mechanism for maintaining a queue of ready or available processes linked together according to an assigned priority for a plurality of central processors where the processors may be assigned to the highest priority task when that processor is not busy executing some higher priority task. The task control mechanism also includes a mechanism for computing task priorities as new tasks are inserted into the queue or removed. The mechanism also maintains an event table which is really a table of event designations to be allocated to different processes upon request where the requesting processes assign a particular function or "meaning" to the event designation. The mechanism of the present invention maintains the state of such allocated events in the event table and signals the related (or "waiting") processes that an event has happened so that the particular system central processors assigned to execute those particular processes may then proceed with their execution.

Abstract: An apparatus for digitally storing samples of a received signal having a carrier frequency component and an angle modulation component and for subsequently reconstructing such received signal from the stored samples. The system includes a pair of digital memory systems, a first one storing samples of a signal fed thereto at a relatively high rate, and a second one storing samples of a signal fed thereto at a relatively low rate. The received signal is coupled to the first memory system for a relatively short period of time for storing therein samples representative of the carrier frequency component. The received signal is also coupled to the second memory system for a relatively long period of time for storing therein samples representative of the angle modulation component.

Abstract: A real time controller is described for obtaining real time data from a sensor incorporating a memory, comparator, instruction decoder and real time counter. The real time controller solves the problem of gathering real time data as a function of time from a plurality of sensors receiving a plurality of signals.